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Instead of having one "god" circuit, we now have specialized circuits for access control, bus ordering logic, address offset calculation, and meta data generation. This frees up the "core" logic of the register to `registerC`, which now only decides when and what to write.
This will later be used to determine whether registers need a lock inserted or not.
This commit extends the current `registerWb` with an (optional) lock register that can be used by the software to either atomically read or write from/to a register. By default, the register decides to include a lock register or not by reasoning about whether the software would (in practice) write to it in multiple bus accesses or not. Users can opt-out of a lock register by passing `lock = NoLock` to `registerConfig`.
In a separate commit, because I'm not convinced we should merge as is. If we do, we should make an issue to clean this up.
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This PR extends the current
registerWbwith an (optional) lock register that can be used by the software to either atomically read or write from/to a register. By default, the register decides to include a lock register or not by reasoning about whether the software would (in practice) write to it in multiple bus accesses or not. Users can opt-out of a lock register by passinglock = NoLocktoregisterConfig.TODO
clash-protocols-memmap/tests/Tests/Protocols/MemoryMap/Registers/WishboneStandard.hs. This was mostly vibe-coded, so now it's an endless nesting of if-then-elses.Freezetest.