Bpaczek/misra pr

.github/workflows/ci.yml

@@ -14,9 +14,13 @@ on:
       - 'bpaczek/*'
 
 
+
 jobs:
   call-ci:
-    uses: bartekpaczek/phoenix-rtos-project-fork/.github/workflows/ci-submodule.yml@bpaczek/misra-ci
+    uses: bartekpaczek/phoenix-rtos-project-fork/.github/workflows/ci-submodule.yml@master
     secrets: inherit
     with:
       build_params: all tests
+
+
+

hal/aarch64/zynqmp/zynqmp.c

@@ -63,17 +63,6 @@ int _interrupts_gicv2_classify(unsigned int irqn)
 }
 
 
-static int _zynqmp_getActiveBitShift(int dev)
-{
-	if ((dev >= pctl_devclock_lpd_usb3_dual) && (dev <= pctl_devclock_lpd_usb1_bus)) {
-		return 25;
-	}
-	else {
-		return 24;
-	}
-}
-
-
 static int _zynqmp_setBasicGenerator(volatile u32 *reg, int dev, char src, char div0, char div1, char active)
 {
 	u32 val = src;
@@ -84,7 +73,7 @@ static int _zynqmp_setBasicGenerator(volatile u32 *reg, int dev, char src, char
 		val &= 0x3;
 	}
 
-	val |= ((div0 & 0x3f) << 8) | ((div1 & 0x3f) << 16) | (active << _zynqmp_getActiveBitShift(dev));
+	val |= ((div0 & 0x3f) << 8) | ((div1 & 0x3f) << 16) | (active << 24);
 	if (dev == pctl_devclock_lpd_cpu_r5) {
 		/* According to docs turning this bit off could lead to system hang - ensure it is on */
 		val |= (1 << 24);
@@ -111,13 +100,13 @@ int _zynqmp_setDevClock(int dev, char src, char div0, char div1, char active)
 }
 
 
-static int _zynqmp_getBasicGenerator(int dev, volatile u32 *reg, char *src, char *div0, char *div1, char *active)
+static int _zynqmp_getBasicGenerator(volatile u32 *reg, char *src, char *div0, char *div1, char *active)
 {
 	u32 val = *reg;
 	*src = val & 0x7;
 	*div0 = (val >> 8) & 0x3f;
 	*div1 = (val >> 16) & 0x3f;
-	*active = val >> _zynqmp_getActiveBitShift(dev);
+	*active = val >> 24;
 	return 0;
 }
 
@@ -126,11 +115,11 @@ int _zynqmp_getDevClock(int dev, char *src, char *div0, char *div1, char *active
 {
 	if ((dev >= pctl_devclock_lpd_usb3_dual) && (dev <= pctl_devclock_lpd_timestamp)) {
 		unsigned regOffset = (dev - pctl_devclock_lpd_usb3_dual) + crl_apb_usb3_dual_ref_ctrl;
-		return _zynqmp_getBasicGenerator(dev, zynq_common.crl_apb + regOffset, src, div0, div1, active);
+		return _zynqmp_getBasicGenerator(zynq_common.crl_apb + regOffset, src, div0, div1, active);
 	}
 	else if ((dev >= pctl_devclock_fpd_acpu) && (dev <= pctl_devclock_fpd_dbg_tstmp)) {
 		unsigned regOffset = (dev - pctl_devclock_fpd_acpu) + crf_apb_acpu_ctrl;
-		return _zynqmp_getBasicGenerator(dev, zynq_common.crf_apb + regOffset, src, div0, div1, active);
+		return _zynqmp_getBasicGenerator(zynq_common.crf_apb + regOffset, src, div0, div1, active);
 	}
 
 	return -1;
@@ -413,7 +402,7 @@ int hal_platformctl(void *ptr)
 		case pctl_devclock:
 			if (data->action == pctl_set)
 				ret = _zynqmp_setDevClock(data->devclock.dev, data->devclock.src, data->devclock.div0, data->devclock.div1, data->devclock.active);
-			else if (data->action == pctl_get)
+			else if (data->action == pctl_set)
 				ret = _zynqmp_getDevClock(data->devclock.dev, &data->devclock.src, &data->devclock.div0, &data->devclock.div1, &data->devclock.active);
 			break;
 

hal/arm/scs.c

@@ -95,18 +95,18 @@ static struct {
 } scs_common;
 
 
-void _hal_scsIRQSet(u32 irqn, u8 state)
+void _hal_scsIRQSet(s8 irqn, u8 state)
 {
 	volatile u32 *ptr = (state != 0) ? scs_common.scs->iser : scs_common.scs->icer;
 
-	*(ptr + (irqn / 32)) = 1u << (irqn % 32);
+	*(ptr + ((u8)irqn >> 5)) = 1u << (irqn & 0x1f);
 
 	hal_cpuDataSyncBarrier();
 	hal_cpuInstrBarrier();
 }
 
 
-void _hal_scsIRQPrioritySet(u32 irqn, u32 priority)
+void _hal_scsIRQPrioritySet(s8 irqn, u32 priority)
 {
 	volatile u8 *ptr = (volatile u8 *)scs_common.scs->ip;
 
@@ -117,28 +117,28 @@ void _hal_scsIRQPrioritySet(u32 irqn, u32 priority)
 }
 
 
-void _hal_scsIRQPendingSet(u32 irqn)
+void _hal_scsIRQPendingSet(s8 irqn)
 {
 	volatile u32 *ptr = scs_common.scs->ispr;
 
-	*(ptr + (irqn / 32)) = 1u << (irqn % 32);
+	*(ptr + ((u8)irqn >> 5)) = 1u << (irqn & 0x1f);
 
 	hal_cpuDataSyncBarrier();
 	hal_cpuInstrBarrier();
 }
 
 
-int _hal_scsIRQPendingGet(u32 irqn)
+int _hal_scsIRQPendingGet(s8 irqn)
 {
-	volatile u32 *ptr = &scs_common.scs->ispr[irqn / 32];
-	return ((*ptr & (1 << (irqn % 32))) != 0) ? 1 : 0;
+	volatile u32 *ptr = &scs_common.scs->ispr[(u8)irqn >> 5];
+	return ((*ptr & (1 << (irqn & 0x1f))) != 0) ? 1 : 0;
 }
 
 
-int _hal_scsIRQActiveGet(u32 irqn)
+int _hal_scsIRQActiveGet(s8 irqn)
 {
-	volatile u32 *ptr = &scs_common.scs->iabr[irqn / 32];
-	return ((*ptr & (1 << (irqn % 32))) != 0) ? 1 : 0;
+	volatile u32 *ptr = &scs_common.scs->iabr[(u8)irqn >> 5];
+	return ((*ptr & (1 << (irqn & 0x1f))) != 0) ? 1 : 0;
 }
 
 
@@ -162,7 +162,7 @@ u32 _hal_scsPriorityGroupingGet(void)
 }
 
 
-void _hal_scsExceptionPrioritySet(u32 excpn, u32 priority)
+void _hal_scsExceptionPrioritySet(s8 excpn, u32 priority)
 {
 	volatile u8 *ptr = (u8 *)&scs_common.scs->shpr1 + excpn - 4;
 
@@ -171,7 +171,7 @@ void _hal_scsExceptionPrioritySet(u32 excpn, u32 priority)
 }
 
 
-u32 _imxrt_scsExceptionPriorityGet(u32 excpn)
+u32 _imxrt_scsExceptionPriorityGet(s8 excpn)
 {
 	volatile u8 *ptr = (u8 *)&scs_common.scs->shpr1 + excpn - 4;
 
@@ -409,12 +409,6 @@ u32 _hal_scsSystickGetCount(u8 *overflow_out)
 }
 
 
-u32 _hal_scsGetDefaultFPSCR(void)
-{
-	return scs_common.scs->fpdscr;
-}
-
-
 void _hal_scsInit(void)
 {
 	scs_common.scs = (void *)0xe000e000;

hal/arm/scs.h

@@ -21,19 +21,19 @@
 #include "hal/types.h"
 
 
-void _hal_scsIRQSet(u32 irqn, u8 state);
+void _hal_scsIRQSet(s8 irqn, u8 state);
 
 
-void _hal_scsIRQPrioritySet(u32 irqn, u32 priority);
+void _hal_scsIRQPrioritySet(s8 irqn, u32 priority);
 
 
-void _hal_scsIRQPendingSet(u32 irqn);
+void _hal_scsIRQPendingSet(s8 irqn);
 
 
-int _hal_scsIRQPendingGet(u32 irqn);
+int _hal_scsIRQPendingGet(s8 irqn);
 
 
-int _hal_scsIRQActiveGet(u32 irqn);
+int _hal_scsIRQActiveGet(s8 irqn);
 
 
 void _hal_scsPriorityGroupingSet(u32 group);
@@ -42,10 +42,10 @@ void _hal_scsPriorityGroupingSet(u32 group);
 u32 _hal_scsPriorityGroupingGet(void);
 
 
-void _hal_scsExceptionPrioritySet(u32 excpn, u32 priority);
+void _hal_scsExceptionPrioritySet(s8 excpn, u32 priority);
 
 
-u32 _imxrt_scsExceptionPriorityGet(u32 excpn);
+u32 _imxrt_scsExceptionPriorityGet(s8 excpn);
 
 
 void _hal_scsSystemReset(void);
@@ -91,11 +91,6 @@ void _hal_scsSystickInit(u32 load);
 u32 _hal_scsSystickGetCount(u8 *overflow_out);
 
 
-/* Get the value to use for FPSCR when creating a new context.
- * It is stored in FPDSCR register. */
-u32 _hal_scsGetDefaultFPSCR(void);
-
-
 void _hal_scsInit(void);
 
 

hal/armv8m/arch/cpu.h

@@ -28,31 +28,12 @@
 #define SIZE_KSTACK (4U * SIZE_PAGE)
 #endif
 
-/* If KERNEL_FPU_SUPPORT == 0, FPU/MVE context handling in the kernel will be disabled.
- * This flag must be set externally to 1 by the build system to enable FPU handling. */
-#ifndef KERNEL_FPU_SUPPORT
-#define KERNEL_FPU_SUPPORT 0
-#endif
-
 /* values based on EXC_RETURN requirements */
-#define EXC_RETURN_SPSEL (1u << 2) /* 1 - was using process SP, 0 - was using main SP */
-#define EXC_RETURN_FTYPE (1u << 4) /* 1 - standard frame, 0 - frame with FPU state */
-
-#define DEFAULT_PSR 0x01000000
-
-#if KERNEL_FPU_SUPPORT
-#define RET_HANDLER_MSP 0xffffffe1u
-#define RET_THREAD_MSP  0xffffffe9u
-#define RET_THREAD_PSP  0xffffffedu
-#define HWCTXSIZE       (8 + 18)
-#define USERCONTROL     0x7u
-#else
 #define RET_HANDLER_MSP 0xfffffff1u
 #define RET_THREAD_MSP  0xfffffff9u
 #define RET_THREAD_PSP  0xfffffffdu
 #define HWCTXSIZE       8
 #define USERCONTROL     0x3u
-#endif
 
 #ifndef __ASSEMBLY__
 
@@ -87,7 +68,7 @@ typedef struct {
 
 typedef struct _cpu_context_t {
 	u32 savesp_s;
-	u32 fpuctx; /* If KERNEL_FPU_SUPPORT == 0 fpuctx is unused, otherwise it is the value of FPCAR at exception entry. */
+	u32 padding;
 
 	/* Saved by ISR */
 	u32 psp;
@@ -104,48 +85,9 @@ typedef struct _cpu_context_t {
 	u32 msp;
 	u32 pad0;
 
-#if KERNEL_FPU_SUPPORT
-	u32 s16;
-	u32 s17;
-	u32 s18;
-	u32 s19;
-	u32 s20;
-	u32 s21;
-	u32 s22;
-	u32 s23;
-	u32 s24;
-	u32 s25;
-	u32 s26;
-	u32 s27;
-	u32 s28;
-	u32 s29;
-	u32 s30;
-	u32 s31;
-#endif
-
 	/* Saved by hardware */
 	cpu_hwContext_t hwctx;
 
-#if KERNEL_FPU_SUPPORT
-	u32 s0;
-	u32 s1;
-	u32 s2;
-	u32 s3;
-	u32 s4;
-	u32 s5;
-	u32 s6;
-	u32 s7;
-	u32 s8;
-	u32 s9;
-	u32 s10;
-	u32 s11;
-	u32 s12;
-	u32 s13;
-	u32 s14;
-	u32 s15;
-	u32 fpscr;
-	u32 vpr;
-#endif
 } cpu_context_t;
 
 

hal/armv8m/cpu.c

@@ -111,19 +111,11 @@ int hal_cpuCreateContext(cpu_context_t **nctx, void (*start)(void *harg), void *
 	ctx->hwctx.r12 = 0xcccccccc;
 	ctx->hwctx.lr = 0xeeeeeeee;
 	ctx->hwctx.pc = (u32)start;
-	ctx->hwctx.psr = DEFAULT_PSR;
+	ctx->hwctx.psr = 0x01000000;
 	if (ustack != NULL) {
-#if KERNEL_FPU_SUPPORT
-		ctx->fpuctx = ctx->psp + (8 * sizeof(u32)); /* Must point to s0 in hw-saved context */
-		ctx->fpscr = _hal_scsGetDefaultFPSCR();
-#endif
 		ctx->irq_ret = RET_THREAD_PSP;
 	}
 	else {
-#if KERNEL_FPU_SUPPORT
-		ctx->fpuctx = (u32)(&ctx->hwctx) + (8 * sizeof(u32)); /* Must point to s0 in hw-saved context */
-		ctx->fpscr = _hal_scsGetDefaultFPSCR();
-#endif
 		ctx->irq_ret = RET_THREAD_MSP;
 	}
 
@@ -152,7 +144,7 @@ int hal_cpuPushSignal(void *kstack, void (*handler)(void), cpu_context_t *signal
 	signalCtx->hwctx.pc = (u32)handler;
 
 	/* Set default PSR, clear potential ICI/IT flags */
-	signalCtx->hwctx.psr = DEFAULT_PSR;
+	signalCtx->hwctx.psr = 0x01000000;
 
 	if (src == SIG_SRC_SCHED) {
 		/* We'll be returning through interrupt dispatcher,
@@ -225,12 +217,7 @@ char *hal_cpuInfo(char *info)
 char *hal_cpuFeatures(char *features, unsigned int len)
 {
 	unsigned int n = 0;
-#if KERNEL_FPU_SUPPORT
-	if ((len - n) > 5) {
-		hal_strcpy(features + n, "FPU, ");
-		n += 5;
-	}
-#else
+#ifdef CPU_NRF91
 	if ((len - n) > 8) {
 		hal_strcpy(features + n, "softfp, ");
 		n += 8;
@@ -270,9 +257,9 @@ void hal_cpuReboot(void)
 }
 
 
+/* TODO: add implementation */
 void hal_cleanDCache(ptr_t start, size_t len)
 {
-	_hal_scsDCacheCleanAddr((void *)start, len);
 }