Refactored to be able to load TIS100 instructions at

runtime

Author: axlan

README.md

@@ -106,7 +106,7 @@ positional arguments:
 
 optional arguments:
   -h, --help            show this help message and exit
-  -t {memh,memb,csvb,coeh,pick}, --type {memh,memb,csvb,coeh,pick}
+  -t {memh,memb,csvb,coeh,pick}, --type {memh,memb,csvb,coeh,pick, cu32}
                         sets output type
   -o OUT_FILE, --out_file OUT_FILE
                         sets output file path
@@ -121,6 +121,7 @@ The current output formats are:
  * csvb - memb, but each portion of instruction separated by comma
  * coeh - Xilinx coefficients file, see [here](https://www.xilinx.com/support/documentation/sw_manuals/xilinx11/cgn_r_coe_file_syntax.htm)
  * pick - python pickle used for emulator
+ * cu32 - a c array of 32 bit unsigned values. This is used to load instruction onto the TIS100 from the ARM CPU.
 
 For example to compile the multiplier code for the emulator:
 
@@ -147,13 +148,13 @@ To run on real hardware:
 
 - [x] Connect multiple nodes together using top level design file
 - [x] Connect to ARM in Zynq SoC over AXI (use as co-processor)
-- [ ] Have ability to view contents, load code, input, output
+- [x] Have ability to load code
 - [x] Be able to wire up in Xilinx Block designer
+- [ ] Set up a monitoring/control UI
 - [ ] Build from Lua Script
 
 # Misc Todo
 
 - [ ] Refactor Testbenches to use tasks for code reuse
 - [ ] Add ANY and LAST targets for data (use 4 cycles to avoid multiple writes or reads to same node)
 - [ ] Improve testbench simulations to avoid needing to fully recompile each time (compile library?)
-- [ ] Comment and clean up code

build.tcl

@@ -3,7 +3,7 @@
 #
 # build.tcl: Tcl script for re-creating project 'tis100'
 #
-# Generated by Vivado on Mon Feb 24 00:44:55 -0800 2020
+# Generated by Vivado on Mon Feb 24 12:37:34 -0800 2020
 # IP Build 2700528 on Thu Nov  7 00:09:20 MST 2019
 #
 # This file contains the Vivado Tcl commands for re-creating the project to the state*
@@ -23,7 +23,7 @@
 # 2. The following source(s) files that were local or imported into the original project.
 #    (Please see the '$orig_proj_dir' and '$origin_dir' variable setting below at the start of the script)
 #
-#    "C:/Users/A/tis100/tis100/tis100.srcs/sources_1/bd/design_top/design_top.bd"
+#    <none>
 #
 # 3. The following remote source files that were added to the original project:-
 #
@@ -32,7 +32,7 @@
 #    "C:/Users/A/tis100/data/seq_gen/seq_gen_ina.mem"
 #    "C:/Users/A/tis100/src/ip/tis100_1.0/src/my_params.vh"
 #    "C:/Users/A/tis100/data/dir_manager_tv.mem"
-#    "C:/Users/A/tis100/data/instr_ram_tv.mem"
+#    "C:/Users/A/tis100/data/instr_rom_tv.mem"
 #    "C:/Users/A/tis100/data/seq_gen/seq_gen_node2.mem"
 #    "C:/Users/A/tis100/data/test_mult.mem"
 #    "C:/Users/A/tis100/data/registers_tv.mem"
@@ -41,6 +41,7 @@
 #    "C:/Users/A/tis100/data/op_decode_tv.mem"
 #    "C:/Users/A/tis100/data/alu_tv.mem"
 #    "C:/Users/A/tis100/data/test_opcodes.mem"
+#    "C:/Users/A/tis100/src/sim/axi_tis_rw_tb.v"
 #    "C:/Users/A/tis100/src/sim/op_decode_tb.v"
 #    "C:/Users/A/tis100/src/sim/t21_node_tb.v"
 #    "C:/Users/A/tis100/src/sim/t21_2_node_tb.v"
@@ -51,9 +52,11 @@
 #    "C:/Users/A/tis100/src/ip/tis100_1.0/src/op_decode.v"
 #    "C:/Users/A/tis100/src/sim/registers_tb.v"
 #    "C:/Users/A/tis100/src/sim/instr_ram_tb.v"
+#    "C:/Users/A/tis100/src/sim/instr_rom_tb.v"
 #    "C:/Users/A/tis100/src/sim/dir_manager_tb.v"
 #    "C:/Users/A/tis100/src/ip/tis100_1.0/src/instr_ram.v"
 #    "C:/Users/A/tis100/src/ip/tis100_1.0/src/registers.v"
+#    "C:/Users/A/tis100/src/ip/tis100_1.0/hdl/tis100_v1_0_S00_AXI.v"
 #
 #*****************************************************************************************
 
@@ -179,6 +182,7 @@ add_files -norecurse -fileset $obj $files
 # Set 'sources_1' fileset properties
 set obj [get_filesets sources_1]
 set_property -name "top" -value "design_top_wrapper" -objects $obj
+set_property -name "top_auto_set" -value "0" -objects $obj
 
 # Create 'constrs_1' fileset (if not found)
 if {[string equal [get_filesets -quiet constrs_1] ""]} {
@@ -214,6 +218,7 @@ set files [list \
  [file normalize "${origin_dir}/data/op_decode_tv.mem"] \
  [file normalize "${origin_dir}/data/alu_tv.mem"] \
  [file normalize "${origin_dir}/data/test_opcodes.mem"] \
+ [file normalize "${origin_dir}/src/sim/axi_tis_rw_tb.v"] \
  [file normalize "${origin_dir}/src/sim/op_decode_tb.v"] \
  [file normalize "${origin_dir}/src/sim/t21_node_tb.v"] \
  [file normalize "${origin_dir}/src/sim/t21_2_node_tb.v"] \
@@ -228,12 +233,84 @@ set files [list \
  [file normalize "${origin_dir}/src/sim/dir_manager_tb.v"] \
  [file normalize "${origin_dir}/src/ip/tis100_1.0/src/instr_ram.v"] \
  [file normalize "${origin_dir}/src/ip/tis100_1.0/src/registers.v"] \
+ [file normalize "${origin_dir}/src/ip/tis100_1.0/hdl/tis100_v1_0_S00_AXI.v"] \
 ]
 add_files -norecurse -fileset $obj $files
 
+# Set 'sim_1' fileset file properties for remote files
+set file "$origin_dir/data/seq_gen/seq_gen_inb.mem"
+set file [file normalize $file]
+set file_obj [get_files -of_objects [get_filesets sim_1] [list "*$file"]]
+set_property -name "file_type" -value "Memory File" -objects $file_obj
+
+set file "$origin_dir/data/seq_gen/seq_gen_ina.mem"
+set file [file normalize $file]
+set file_obj [get_files -of_objects [get_filesets sim_1] [list "*$file"]]
+set_property -name "file_type" -value "Memory File" -objects $file_obj
+
+set file "$origin_dir/src/ip/tis100_1.0/src/my_params.vh"
+set file [file normalize $file]
+set file_obj [get_files -of_objects [get_filesets sim_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog Header" -objects $file_obj
+
+set file "$origin_dir/data/dir_manager_tv.mem"
+set file [file normalize $file]
+set file_obj [get_files -of_objects [get_filesets sim_1] [list "*$file"]]
+set_property -name "file_type" -value "Memory File" -objects $file_obj
+
+set file "$origin_dir/data/instr_rom_tv.mem"
+set file [file normalize $file]
+set file_obj [get_files -of_objects [get_filesets sim_1] [list "*$file"]]
+set_property -name "file_type" -value "Memory File" -objects $file_obj
+
+set file "$origin_dir/data/seq_gen/seq_gen_node2.mem"
+set file [file normalize $file]
+set file_obj [get_files -of_objects [get_filesets sim_1] [list "*$file"]]
+set_property -name "file_type" -value "Memory File" -objects $file_obj
+
+set file "$origin_dir/data/test_mult.mem"
+set file [file normalize $file]
+set file_obj [get_files -of_objects [get_filesets sim_1] [list "*$file"]]
+set_property -name "file_type" -value "Memory File" -objects $file_obj
+
+set file "$origin_dir/data/registers_tv.mem"
+set file [file normalize $file]
+set file_obj [get_files -of_objects [get_filesets sim_1] [list "*$file"]]
+set_property -name "file_type" -value "Memory File" -objects $file_obj
+
+set file "$origin_dir/data/seq_gen/seq_gen_result.mem"
+set file [file normalize $file]
+set file_obj [get_files -of_objects [get_filesets sim_1] [list "*$file"]]
+set_property -name "file_type" -value "Memory File" -objects $file_obj
+
+set file "$origin_dir/data/seq_gen/seq_gen_node1.mem"
+set file [file normalize $file]
+set file_obj [get_files -of_objects [get_filesets sim_1] [list "*$file"]]
+set_property -name "file_type" -value "Memory File" -objects $file_obj
+
+set file "$origin_dir/data/op_decode_tv.mem"
+set file [file normalize $file]
+set file_obj [get_files -of_objects [get_filesets sim_1] [list "*$file"]]
+set_property -name "file_type" -value "Memory File" -objects $file_obj
+
+set file "$origin_dir/data/alu_tv.mem"
+set file [file normalize $file]
+set file_obj [get_files -of_objects [get_filesets sim_1] [list "*$file"]]
+set_property -name "file_type" -value "Memory File" -objects $file_obj
+
+set file "$origin_dir/data/test_opcodes.mem"
+set file [file normalize $file]
+set file_obj [get_files -of_objects [get_filesets sim_1] [list "*$file"]]
+set_property -name "file_type" -value "Memory File" -objects $file_obj
+
+
+# Set 'sim_1' fileset file properties for local files
+# None
+
 # Set 'sim_1' fileset properties
 set obj [get_filesets sim_1]
 set_property -name "top" -value "design_top_wrapper" -objects $obj
+set_property -name "top_auto_set" -value "0" -objects $obj
 set_property -name "top_lib" -value "xil_defaultlib" -objects $obj
 
 # Set 'utils_1' fileset object
@@ -388,7 +465,8 @@ proc cr_bd_design_top { parentCell } {
    CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR0 {1} \
    CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR1 {1} \
    CONFIG.PCW_ENET1_RESET_ENABLE {0} \
-   CONFIG.PCW_ENET_RESET_ENABLE {0} \
+   CONFIG.PCW_ENET_RESET_ENABLE {1} \
+   CONFIG.PCW_ENET_RESET_SELECT {Share reset pin} \
    CONFIG.PCW_EN_CLK0_PORT {1} \
    CONFIG.PCW_EN_CLK1_PORT {0} \
    CONFIG.PCW_EN_CLK2_PORT {0} \
@@ -658,8 +736,8 @@ proc cr_bd_design_top { parentCell } {
    CONFIG.PCW_MIO_9_PULLUP {disabled} \
    CONFIG.PCW_MIO_9_SLEW {slow} \
    CONFIG.PCW_MIO_PRIMITIVE {54} \
-   CONFIG.PCW_MIO_TREE_PERIPHERALS {GPIO#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#GPIO#Quad SPI Flash#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#GPIO#UART 1#UART 1#SD 0#GPIO#Enet 0#Enet 0} \
-   CONFIG.PCW_MIO_TREE_SIGNALS {gpio[0]#qspi0_ss_b#qspi0_io[0]#qspi0_io[1]#qspi0_io[2]#qspi0_io[3]/HOLD_B#qspi0_sclk#gpio[7]#qspi_fbclk#gpio[9]#gpio[10]#gpio[11]#gpio[12]#gpio[13]#gpio[14]#gpio[15]#tx_clk#txd[0]#txd[1]#txd[2]#txd[3]#tx_ctl#rx_clk#rxd[0]#rxd[1]#rxd[2]#rxd[3]#rx_ctl#data[4]#dir#stp#nxt#data[0]#data[1]#data[2]#data[3]#clk#data[5]#data[6]#data[7]#clk#cmd#data[0]#data[1]#data[2]#data[3]#cd#gpio[47]#tx#rx#wp#gpio[51]#mdc#mdio} \
+   CONFIG.PCW_MIO_TREE_PERIPHERALS {GPIO#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#USB Reset#Quad SPI Flash#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#GPIO#UART 1#UART 1#SD 0#GPIO#Enet 0#Enet 0} \
+   CONFIG.PCW_MIO_TREE_SIGNALS {gpio[0]#qspi0_ss_b#qspi0_io[0]#qspi0_io[1]#qspi0_io[2]#qspi0_io[3]/HOLD_B#qspi0_sclk#reset#qspi_fbclk#gpio[9]#gpio[10]#gpio[11]#gpio[12]#gpio[13]#gpio[14]#gpio[15]#tx_clk#txd[0]#txd[1]#txd[2]#txd[3]#tx_ctl#rx_clk#rxd[0]#rxd[1]#rxd[2]#rxd[3]#rx_ctl#data[4]#dir#stp#nxt#data[0]#data[1]#data[2]#data[3]#clk#data[5]#data[6]#data[7]#clk#cmd#data[0]#data[1]#data[2]#data[3]#cd#gpio[47]#tx#rx#wp#gpio[51]#mdc#mdio} \
    CONFIG.PCW_NAND_GRP_D8_ENABLE {0} \
    CONFIG.PCW_NAND_PERIPHERAL_ENABLE {0} \
    CONFIG.PCW_NOR_GRP_A25_ENABLE {0} \
@@ -768,11 +846,12 @@ proc cr_bd_design_top { parentCell } {
    CONFIG.PCW_UIPARAM_DDR_USE_INTERNAL_VREF {0} \
    CONFIG.PCW_USB0_PERIPHERAL_ENABLE {1} \
    CONFIG.PCW_USB0_PERIPHERAL_FREQMHZ {60} \
-   CONFIG.PCW_USB0_RESET_ENABLE {0} \
-   CONFIG.PCW_USB0_RESET_IO {<Select>} \
+   CONFIG.PCW_USB0_RESET_ENABLE {1} \
+   CONFIG.PCW_USB0_RESET_IO {MIO 7} \
    CONFIG.PCW_USB0_USB0_IO {MIO 28 .. 39} \
    CONFIG.PCW_USB1_RESET_ENABLE {0} \
-   CONFIG.PCW_USB_RESET_ENABLE {0} \
+   CONFIG.PCW_USB_RESET_ENABLE {1} \
+   CONFIG.PCW_USB_RESET_SELECT {Share reset pin} \
    CONFIG.PCW_USE_AXI_NONSECURE {1} \
    CONFIG.PCW_USE_FABRIC_INTERRUPT {1} \
    CONFIG.PCW_USE_M_AXI_GP0 {1} \
@@ -782,7 +861,7 @@ proc cr_bd_design_top { parentCell } {
   # Create instance: ps7_0_axi_periph, and set properties
   set ps7_0_axi_periph [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 ps7_0_axi_periph ]
   set_property -dict [ list \
-   CONFIG.NUM_MI {2} \
+   CONFIG.NUM_MI {1} \
  ] $ps7_0_axi_periph
 
   # Create instance: rst_ps7_0_100M, and set properties
@@ -796,24 +875,23 @@ proc cr_bd_design_top { parentCell } {
   connect_bd_intf_net -intf_net processing_system7_0_FIXED_IO [get_bd_intf_ports FIXED_IO] [get_bd_intf_pins processing_system7_0/FIXED_IO]
   connect_bd_intf_net -intf_net processing_system7_0_M_AXI_GP0 [get_bd_intf_pins processing_system7_0/M_AXI_GP0] [get_bd_intf_pins ps7_0_axi_periph/S00_AXI]
   connect_bd_intf_net -intf_net ps7_0_axi_periph_M00_AXI [get_bd_intf_pins ps7_0_axi_periph/M00_AXI] [get_bd_intf_pins tis100_0/S00_AXI]
-  connect_bd_intf_net -intf_net ps7_0_axi_periph_M01_AXI [get_bd_intf_pins ps7_0_axi_periph/M01_AXI] [get_bd_intf_pins tis100_0/S_AXI_INTR]
 
   # Create port connections
-  connect_bd_net -net processing_system7_0_FCLK_CLK0 [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] [get_bd_pins ps7_0_axi_periph/ACLK] [get_bd_pins ps7_0_axi_periph/M00_ACLK] [get_bd_pins ps7_0_axi_periph/M01_ACLK] [get_bd_pins ps7_0_axi_periph/S00_ACLK] [get_bd_pins rst_ps7_0_100M/slowest_sync_clk] [get_bd_pins tis100_0/s00_axi_aclk] [get_bd_pins tis100_0/s_axi_intr_aclk]
+  connect_bd_net -net processing_system7_0_FCLK_CLK0 [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] [get_bd_pins ps7_0_axi_periph/ACLK] [get_bd_pins ps7_0_axi_periph/M00_ACLK] [get_bd_pins ps7_0_axi_periph/S00_ACLK] [get_bd_pins rst_ps7_0_100M/slowest_sync_clk] [get_bd_pins tis100_0/s00_axi_aclk]
   connect_bd_net -net processing_system7_0_FCLK_RESET0_N [get_bd_pins processing_system7_0/FCLK_RESET0_N] [get_bd_pins rst_ps7_0_100M/ext_reset_in]
-  connect_bd_net -net rst_ps7_0_100M_peripheral_aresetn [get_bd_pins ps7_0_axi_periph/ARESETN] [get_bd_pins ps7_0_axi_periph/M00_ARESETN] [get_bd_pins ps7_0_axi_periph/M01_ARESETN] [get_bd_pins ps7_0_axi_periph/S00_ARESETN] [get_bd_pins rst_ps7_0_100M/peripheral_aresetn] [get_bd_pins tis100_0/s00_axi_aresetn] [get_bd_pins tis100_0/s_axi_intr_aresetn]
+  connect_bd_net -net rst_ps7_0_100M_peripheral_aresetn [get_bd_pins ps7_0_axi_periph/ARESETN] [get_bd_pins ps7_0_axi_periph/M00_ARESETN] [get_bd_pins ps7_0_axi_periph/S00_ARESETN] [get_bd_pins rst_ps7_0_100M/peripheral_aresetn] [get_bd_pins tis100_0/s00_axi_aresetn]
   connect_bd_net -net tis100_0_irq [get_bd_pins processing_system7_0/IRQ_F2P] [get_bd_pins tis100_0/irq]
 
   # Create address segments
   assign_bd_address -offset 0x43C00000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs tis100_0/S00_AXI/S00_AXI_reg] -force
-  assign_bd_address -offset 0x43C10000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs tis100_0/S_AXI_INTR/S_AXI_INTR_reg] -force
 
 
   # Restore current instance
   current_bd_instance $oldCurInst
 
-  validate_bd_design
   save_bd_design
+common::send_msg_id "BD_TCL-1000" "WARNING" "This Tcl script was generated from a block design that has not been validated. It is possible that design <$design_name> may result in errors during validation."
+
   close_bd_design $design_name 
 }
 # End of cr_bd_design_top()

scripts/compiler.py

@@ -165,6 +165,15 @@ def write_hex_memory_file(hex_file, output_codes):
         lines.append(f'{combined:06x}')
     hex_file.write('\n'.join(lines))
 
+def write_c_u32_array_file(header_file, output_codes):
+    lines = []
+    for output_code in output_codes:
+        combined = output_code_to_int(output_code)
+        lines.append(f'0b{combined:021b}')
+    header_file.write('u32 instrs[] = {\n    ')
+    header_file.write(',\n    '.join(lines))
+    header_file.write('\n};')
+
 def write_hex_coe_file(coe_file, output_codes):
     coe_file.write('memory_initialization_radix = 16;\n')
     coe_file.write('memory_initialization_vector=\n')
@@ -209,7 +218,8 @@ def main(asm_file_name, out_file_name, output_type):
             OutType.memb: write_bin_memory_file,
             OutType.csvb: write_bin_csv_file,
             OutType.coeh: write_hex_coe_file,
-            OutType.pick: write_pickle_file
+            OutType.pick: write_pickle_file,
+            OutType.cu32: write_c_u32_array_file
         }[output_type](fd, output_codes)
 
 class OutType(Enum):
@@ -218,6 +228,7 @@ class OutType(Enum):
     csvb = 'csvb'
     coeh = 'coeh'
     pick = 'pick'
+    cu32 = 'cu32'
     def __str__(self):
         return self.value
 

scripts/run_tests.sh

@@ -6,4 +6,4 @@ source scripts/env.sh
 # xsim  op_decode_tb_behav -key {Behavioral:sim_1:Functional:op_decode_tb} -tclbatch $SCRIPT_PATH/run_tests.tcl -log simulate1.log
 
 vivado -mode batch -source scripts/run_tests.tcl | tee simulation.log
-python scripts/check_sim_logs.py simulation.log 8
+python scripts/check_sim_logs.py simulation.log 9

scripts/run_tests.tcl

@@ -2,7 +2,7 @@ open_project tis100/tis100.xpr
 
 set_property -name {xsim.simulate.runtime} -value {100us} -objects [get_filesets sim_1]
 
-set test_benches {"alu_tb" "op_decode_tb" "registers_tb" "instr_rom_tb" "instr_ram_tb" "dir_manager_tb" "t21_node_tb" "t21_2_node_tb" }
+set test_benches {"alu_tb" "op_decode_tb" "registers_tb" "instr_rom_tb" "instr_ram_tb" "dir_manager_tb" "t21_node_tb" "t21_2_node_tb" "axi_tis_rw_tb" }
 
 foreach test_bench $test_benches {
     set_property top $test_bench [get_filesets sim_1]