Added mechanism for loading instructions in RAM

Author: axlan

build.tcl

@@ -32,7 +32,7 @@
 #    "C:/Users/A/tis100/data/seq_gen/seq_gen_ina.mem"
 #    "C:/Users/A/tis100/src/ip/tis100_1.0/src/my_params.vh"
 #    "C:/Users/A/tis100/data/dir_manager_tv.mem"
-#    "C:/Users/A/tis100/data/instr_rom_tv.mem"
+#    "C:/Users/A/tis100/data/instr_ram_tv.mem"
 #    "C:/Users/A/tis100/data/seq_gen/seq_gen_node2.mem"
 #    "C:/Users/A/tis100/data/test_mult.mem"
 #    "C:/Users/A/tis100/data/registers_tv.mem"
@@ -50,9 +50,9 @@
 #    "C:/Users/A/tis100/src/sim/alu_tb.v"
 #    "C:/Users/A/tis100/src/ip/tis100_1.0/src/op_decode.v"
 #    "C:/Users/A/tis100/src/sim/registers_tb.v"
-#    "C:/Users/A/tis100/src/sim/instr_rom_tb.v"
+#    "C:/Users/A/tis100/src/sim/instr_ram_tb.v"
 #    "C:/Users/A/tis100/src/sim/dir_manager_tb.v"
-#    "C:/Users/A/tis100/src/ip/tis100_1.0/src/instr_rom.v"
+#    "C:/Users/A/tis100/src/ip/tis100_1.0/src/instr_ram.v"
 #    "C:/Users/A/tis100/src/ip/tis100_1.0/src/registers.v"
 #
 #*****************************************************************************************
@@ -223,9 +223,10 @@ set files [list \
  [file normalize "${origin_dir}/src/sim/alu_tb.v"] \
  [file normalize "${origin_dir}/src/ip/tis100_1.0/src/op_decode.v"] \
  [file normalize "${origin_dir}/src/sim/registers_tb.v"] \
+ [file normalize "${origin_dir}/src/sim/instr_ram_tb.v"] \
  [file normalize "${origin_dir}/src/sim/instr_rom_tb.v"] \
  [file normalize "${origin_dir}/src/sim/dir_manager_tb.v"] \
- [file normalize "${origin_dir}/src/ip/tis100_1.0/src/instr_rom.v"] \
+ [file normalize "${origin_dir}/src/ip/tis100_1.0/src/instr_ram.v"] \
  [file normalize "${origin_dir}/src/ip/tis100_1.0/src/registers.v"] \
 ]
 add_files -norecurse -fileset $obj $files

scripts/run_tests.sh

@@ -6,4 +6,4 @@ source scripts/env.sh
 # xsim  op_decode_tb_behav -key {Behavioral:sim_1:Functional:op_decode_tb} -tclbatch $SCRIPT_PATH/run_tests.tcl -log simulate1.log
 
 vivado -mode batch -source scripts/run_tests.tcl | tee simulation.log
-python scripts/check_sim_logs.py simulation.log 7
+python scripts/check_sim_logs.py simulation.log 8

scripts/run_tests.tcl

@@ -2,7 +2,7 @@ open_project tis100/tis100.xpr
 
 set_property -name {xsim.simulate.runtime} -value {100us} -objects [get_filesets sim_1]
 
-set test_benches {"alu_tb" "op_decode_tb" "registers_tb" "instr_rom_tb" "dir_manager_tb" "t21_node_tb" "t21_2_node_tb" }
+set test_benches {"alu_tb" "op_decode_tb" "registers_tb" "instr_rom_tb" "instr_ram_tb" "dir_manager_tb" "t21_node_tb" "t21_2_node_tb" }
 
 foreach test_bench $test_benches {
     set_property top $test_bench [get_filesets sim_1]

src/ip/tis100_1.0/component.xml

@@ -1325,7 +1325,7 @@
         <spirit:fileType>verilogSource</spirit:fileType>
       </spirit:file>
       <spirit:file>
-        <spirit:name>src/instr_rom.v</spirit:name>
+        <spirit:name>src/instr_ram.v</spirit:name>
         <spirit:fileType>verilogSource</spirit:fileType>
       </spirit:file>
       <spirit:file>
@@ -1374,7 +1374,7 @@
         <spirit:fileType>verilogSource</spirit:fileType>
       </spirit:file>
       <spirit:file>
-        <spirit:name>src/instr_rom.v</spirit:name>
+        <spirit:name>src/instr_ram.v</spirit:name>
         <spirit:fileType>verilogSource</spirit:fileType>
       </spirit:file>
       <spirit:file>

src/ip/tis100_1.0/src/instr_rom.v renamed to src/ip/tis100_1.0/src/instr_ram.v

@@ -1,8 +1,8 @@
 `timescale 1ns / 1ps
 
-// module to read instructions from rom and control program counter jumps
+// module to read/write instructions from ram and control program counter jumps
 
-module instr_rom(
+module instr_ram(
         // synchronize with posedge of clk
         input clk,
         // only update values when clk_en is high
@@ -15,17 +15,26 @@ module instr_rom(
         input signed [10:0] acc,
         // address to jump to if jump is performed
         input signed [10:0] jmp_off,
+        // controls whether to write a new instruction
+        input write_en,
+        // address to write new instruction
+        input [4:0] write_addr,
+        // new instruction to write.
+            //Writes must end with highest address instruction.
+        input [20:0] write_data,
         // instruction at current program counter
         output [20:0] opcode
     );
     `include "my_params.vh"
-    // memory file to initialize ROM with
+    // memory file to initialize RAM with
     parameter MEM_INIT_FILE = "";
-    // number of valid instructions in ROM
+    // number of valid instructions in MEM_INIT_FILE
     parameter NUM_ENTRIES = 5'd10;
 
     // memory for storing instructinos
     reg [20:0] ram[31:0];
+    // number of valid instructions in RAM
+    reg [4:0] num_entries;
 
     // program counter pointing to current instruction
     reg [4:0] pc;
@@ -51,6 +60,7 @@ module instr_rom(
     initial begin
         if (MEM_INIT_FILE != "") begin
             $readmemb(MEM_INIT_FILE, ram);
+            num_entries = NUM_ENTRIES;
         end
     end
 
@@ -68,9 +78,9 @@ module instr_rom(
                 begin
                     pc <= 0;
                 end
-                else if (pc_jmp >= NUM_ENTRIES)
+                else if (pc_jmp >= num_entries)
                 begin
-                    pc <= NUM_ENTRIES - 1;
+                    pc <= num_entries - 1;
                 end
                 else
                 begin
@@ -79,7 +89,7 @@ module instr_rom(
             end
             else
             begin
-                if (pc == NUM_ENTRIES - 1)
+                if (pc == num_entries - 1)
                 begin
                     pc <= 0;
                 end
@@ -89,6 +99,11 @@ module instr_rom(
                 end
             end
         end
+        if (write_en)
+        begin
+            ram[write_addr] <= write_data;
+            num_entries <= write_addr + 5'd1;
+        end
     end
 
 endmodule

src/ip/tis100_1.0/src/t21_node.v

@@ -89,7 +89,7 @@ module t21_node(
     op_decode op_decode_0(op_code, src, const, dst, pc_instr, alu_instr, registers_instr, in_mux_sel, out_mux_sel);
 
     alu alu_0(alu_instr, acc_reg, src_input, alu_output);
-    instr_rom #(MEM_INIT_FILE, NUM_ENTRIES)  instr_rom_0(clk, clk_en, reset, pc_instr, acc_reg, src_input, op_code);
+    instr_ram #(MEM_INIT_FILE, NUM_ENTRIES)  instr_ram_0(clk, clk_en, reset, pc_instr, acc_reg, src_input, 1'd0, 5'd0, 21'd0, op_code);
     registers registers_0(clk, clk_en, reset, registers_instr, dst_output, acc_reg);
 
     assign src_input = (in_mux_sel == IN_MUX_SEL_CONST) ? const :

src/sim/instr_ram_tb.v

@@ -0,0 +1,70 @@
+`timescale 1ns / 1ps
+
+module instr_ram_tb();
+reg clk, reset, clk_en;
+reg write_en;
+reg [4:0] write_addr;
+reg [20:0] write_data;
+reg [3:0] op;
+reg signed [10:0] acc, jmp_off;
+reg [20:0] out_expected;
+wire [20:0] out;
+reg [31:0] vectornum, errors;
+reg [20:0] testinstrs [31:0];
+reg [46:0] testvectors [10000:0];
+
+// instantiate device under test
+instr_ram dut(clk, clk_en, reset, op, acc, jmp_off, write_en, write_addr, write_data, out);
+
+// generate clock
+always
+    begin
+        clk = 1; #5; clk = 0; #5;
+    end
+
+// at start of test, load vectors
+// and pulse reset
+initial
+begin
+    $readmemb("instr_rom_tv.mem", testvectors);
+    $readmemb("test_opcodes.mem", testinstrs);
+    vectornum = 0; errors = 0;
+
+    write_en = 0;
+    #5;
+    write_addr = 0;
+    write_en = 1;
+
+    for (write_addr=0; testinstrs[write_addr] !== 21'bx; write_addr = write_addr + 5'd1)
+    begin
+        write_data = testinstrs[write_addr];
+        #10;
+    end
+    write_en = 0;
+
+    clk_en = 0;
+    reset = 1;
+    #10; reset = 0;
+    #12; clk_en = 1;
+end
+
+// check results at falling edge of clock
+always @ (negedge clk)
+begin
+    if (clk_en) begin
+         if (out !== out_expected) begin
+            $display ("Error: input %d", vectornum);
+            $display (" outputs = %d (%d expected)", out, out_expected);
+            errors = errors + 1;
+        end
+        //$display (" %b %b %b %b %b ", a, b, c, d, yexpected);
+        vectornum = vectornum + 1;
+        if (testvectors[vectornum] === 47'bx) begin
+            $display ("%d tests completed with %d errors", vectornum, errors);
+            $finish;
+        end
+    end
+    {op, acc, jmp_off, out_expected} = testvectors[vectornum];
+end
+
+endmodule

src/sim/instr_rom_tb.v

@@ -11,7 +11,7 @@ reg [46:0] testvectors [10000:0];
 
 
 // instantiate device under test
-instr_rom  #("test_opcodes.mem", 10) dut(clk, clk_en, reset, op, acc, jmp_off, out);
+instr_ram  #("test_opcodes.mem", 10) dut(clk, clk_en, reset, op, acc, jmp_off, 1'd0, 5'd0, 21'd0, out);
 
 // generate clock
 always