Osculp32k, Xosc32k: Remove support for a write lock

Write lock is a difficult mechanism to model. In case of a non-POR reset with
a write lock engaged, clocking initialization procedure becomes basically
undefined and types do not reflect the correct state of a hardware. Counter
increment on an `Enabled` type is not enough to model this behaviour correctly.

hal/src/thumbv7em/clock/v2/osculp32k.rs

@@ -22,7 +22,7 @@ use crate::pac::gclk::genctrl::SRC_A;
 use crate::pac::osc32kctrl::rtcctrl::RTCSEL_A;
 use crate::pac::osc32kctrl::OSCULP32K;
 
-use crate::clock::types::{Counter, Enabled, PrivateIncrement};
+use crate::clock::types::{Counter, Enabled};
 use crate::clock::v2::{Source, SourceMarker};
 use crate::time::{Hertz, U32Ext};
 use crate::typelevel::Sealed;
@@ -213,25 +213,6 @@ where
     }
 }
 
-impl<X, Y, N> Enabled<OscUlp32k<X, Y>, N>
-where
-    X: Output32k,
-    Y: Output1k,
-    N: Counter + PrivateIncrement,
-{
-    /// Write lock the OscUlp32k
-    ///
-    /// Locked until a Power-On Reset (POR) is detected.
-    ///
-    /// TODO, how should we model the hardware write lock?
-    /// For now artificially raise the use counter by 1
-    #[inline]
-    pub fn write_lock(mut self) -> <Self as PrivateIncrement>::Inc {
-        self.0.token.wrtlock();
-        self.inc()
-    }
-}
-
 //==============================================================================
 // GclkSource
 //==============================================================================

hal/src/thumbv7em/clock/v2/xosc32k.rs

@@ -20,7 +20,7 @@ use crate::pac::osc32kctrl::xosc32k::{CGM_A, STARTUP_A};
 
 use crate::pac::osc32kctrl::{RegisterBlock, STATUS, XOSC32K};
 
-use crate::clock::types::{Counter, Enabled, PrivateIncrement};
+use crate::clock::types::{Counter, Enabled};
 use crate::clock::v2::{Source, SourceMarker};
 use crate::gpio::v2::{AnyPin, FloatingDisabled, Pin, PA00, PA01};
 use crate::time::{Hertz, U32Ext};
@@ -418,26 +418,6 @@ where
     }
 }
 
-impl<M, X, Y, N> Enabled<Xosc32k<M, X, Y>, N>
-where
-    M: Mode,
-    X: Output32k,
-    Y: Output1k,
-    N: Counter + PrivateIncrement,
-{
-    /// Write lock the Xosc32k
-    ///
-    /// Locked until a Power-On Reset (POR) is detected.
-    ///
-    /// TODO, how should we model the hardware write lock?
-    /// For now artificially raise the use counter by 1
-    #[inline]
-    pub fn write_lock(mut self) -> <Self as PrivateIncrement>::Inc {
-        self.0.token.wrtlock();
-        self.inc()
-    }
-}
-
 impl<M, X, Y> Enabled<Xosc32k<M, X, Y>, U0>
 where
     M: Mode,