Fix bugs and support axvisor to run 2 vms

[liulog]

Axvisor's issue:
arceos-hypervisor/axvisor#303

Features:

• Fix bugs about cause (e.g. modify SupervisorEnvCall to VirtualSupervisorEnvCall )
• Support VS registers load/store at function bind/unbind
• Add decode instruction read from htinst
• Add EID_SRST sbi extension's simple support

Demo:

I run two vms (ArceOS + Linux), both them run in cpu0.

[Copilot]

Pull request overview

This PR enhances the RISC-V hypervisor (axvisor) to support running 2 virtual machines simultaneously by fixing critical bugs and implementing missing features for proper VM context switching.

Key changes:

• Fixed trap cause handling by correcting SupervisorEnvCall to VirtualSupervisorEnvCall and page fault exceptions to their guest equivalents
• Implemented VS-mode CSR save/restore in bind/unbind operations to enable proper vCPU context switching
• Added htinst register decoding support for handling transformed instructions and pseudo-instructions during guest page faults
• Added basic SRST SBI extension support for VM shutdown capability

Reviewed changes

Copilot reviewed 3 out of 3 changed files in this pull request and generated 10 comments.

File	Description
src/vcpu.rs	Core changes including trap cause fixes, VS CSR load/store in bind/unbind, htinst-based instruction decoding, SRST extension handler, and GPR indexing corrections
src/lib.rs	Modified RISCVVCpuCreateConfig to use raw usize for dtb_addr instead of GuestPhysAddr, and exported GprIndex publicly
Cargo.toml	Updated riscv dependency to use a Git repository fork

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[Copilot]

Pull request overview

Copilot reviewed 4 out of 4 changed files in this pull request and generated 5 comments.

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