update toolschain to 2025-05-20, fix naked macro

.github/workflows/ci.yml

@@ -8,7 +8,7 @@ jobs:
     strategy:
       fail-fast: false
       matrix:
-        rust-toolchain: [nightly-2024-12-25, nightly]
+        rust-toolchain: [nightly-2025-05-20, nightly]
         targets: [riscv64gc-unknown-none-elf]
     steps:
     - uses: actions/checkout@v4
@@ -36,7 +36,7 @@ jobs:
     strategy:
       fail-fast: false
       matrix:
-        rust-toolchain: [nightly-2024-12-25]
+        rust-toolchain: [nightly-2025-05-20]
         targets: [riscv64gc-unknown-none-elf]
     permissions:
       contents: write

src/detect.rs

@@ -151,9 +151,8 @@ struct TrapFrame {
 // This function should not be used in conventional trap handling,
 // as it does not preserve a special trap stack, and it's designed to
 // handle exceptions only rather than interrupts.
-#[naked]
+#[unsafe(naked)]
 unsafe extern "C" fn on_detect_trap() -> ! {
-    unsafe {
         naked_asm!(
             ".p2align 2",
             "addi   sp, sp, -8*21",
@@ -213,5 +212,4 @@ unsafe extern "C" fn on_detect_trap() -> ! {
             "sret",
             rust_detect_trap = sym rust_detect_trap,
         )
-    }
 }

src/lib.rs

@@ -1,6 +1,5 @@
 #![no_std]
 #![feature(doc_cfg)]
-#![feature(naked_functions)]
 #![feature(riscv_ext_intrinsics)]
 #![doc = include_str!("../README.md")]
 

src/vcpu.rs

@@ -1,5 +1,3 @@
-use core::ops::{Shl, Shr};
-
 use crate::sbi_console::*;
 use axaddrspace::device::AccessWidth;
 use riscv::register::hstatus;