CHORE: Upgrade doc style action (#855)

* CHORE: Upgrade doc-style action

* REFACTOR: Update skip

* CI: Fix typo

* FIX: Documentation style typos

* FIX: Documentation style typos

.github/workflows/ci_cd.yml

@@ -42,11 +42,9 @@ jobs:
     runs-on: ubuntu-latest
     steps:
       - name: Check documentation style
-        uses: ansys/actions/doc-style@v5
+        uses: ansys/actions/doc-style@v8
         with:
           token: ${{ secrets.GITHUB_TOKEN }}
-          vale-config: "doc/.vale.ini"
-          vale-version: "2.29.6"
 
   smoke-tests:
     name: Build and Smoke tests (${{ matrix.os }} | Python ${{ matrix.python-version }})

.pre-commit-config.yaml

@@ -38,11 +38,12 @@ repos:
     ]
 
 - repo: https://github.com/codespell-project/codespell
-  rev: v2.2.6
+  rev: v2.3.0
   hooks:
   - id: codespell
-    args: ["--toml", "pyproject.toml"]
-    additional_dependencies: [tomli]
+    args: ["--ignore-words", "doc/styles/config/vocabularies/ANSYS/accept.txt"]
+    additional_dependencies:
+      - tomli
 
 - repo: https://github.com/PyCQA/docformatter
   rev: v1.7.5

Makefile

@@ -2,7 +2,7 @@
 
 CODESPELL_DIRS ?= ./src
 CODESPELL_SKIP ?= "*.pyc,*.aedt,*.xml,*.txt,*.gif,*.png,*.jpg,*.js,*.html,*.doctree,*.ttf,*.woff,*.woff2,*.eot,*.mp4,*.inv,*.pickle,*.ipynb,flycheck*,./.git/*,./.hypothesis/*,*.yml,./docs/build/*,./docs/images/*,./dist/*,*~,.hypothesis*,./docs/source/examples/*,*cover,*.dat,*.mac,\#*,PKG-INFO,*.mypy_cache/*,*.xml,*.aedt,*.svg"
-CODESPELL_IGNORE ?= "doc/styles/Vocab/ANSYS/accept.txt"
+CODESPELL_IGNORE ?= "doc/styles/config/vocabularies/ANSYS/accept.txt"
 
 all: doctest flake8
 

doc/source/api/SiWave.rst

@@ -1,6 +1,6 @@
-Siwave manager
+SIwave manager
 ==============
-`Siwave <https://www.ansys.com/products/electronics/ansys-siwave>`_ is a specialized tool
+`SIwave <https://www.ansys.com/products/electronics/ansys-siwave>`_ is a specialized tool
 for power integrity, signal integrity, and EMI analysis of IC packages and PCB. This tool
 solves power delivery systems and high-speed channels in electronic devices. It can be
 accessed from PyEDB in Windows only. All setups can be implemented through EDB API.

doc/source/api/XmlControlFile.rst

@@ -1,6 +1,6 @@
 XML control file
 ================
-Convert a technology file to edb control file.
+Convert a technology file to EDB control file.
 
 
 .. currentmodule:: pyedb.dotnet.edb_core.edb_data.control_file

doc/source/api/edb_data/PortsData.rst

@@ -1,6 +1,6 @@
 Ports
 =====
-These classes are the containers of ports methods of the EDB for both HFSS and Siwave.
+These classes are the containers of ports methods of the EDB for both HFSS and SIwave.
 
 .. autosummary::
    :toctree: _autosummary

doc/source/api/edb_data/SourceData.rst

@@ -1,6 +1,6 @@
 Sources and excitations
 =======================
-These classes are the containers of sources methods of the EDB for both HFSS and Siwave.
+These classes are the containers of sources methods of the EDB for both HFSS and SIwave.
 
 
 .. code:: python

doc/source/api/sim_setup_data/data/siw_dc_ir_settings.rst

@@ -1,6 +1,6 @@
-Siwave DC-IR settings
+SIwave DC-IR settings
 =====================
-This class is the container of Siwave DC-IR settings.
+This class is the container of SIwave DC-IR settings.
 
 
 .. currentmodule:: pyedb.dotnet.edb_core.sim_setup_data.data.siw_dc_ir_settings

doc/source/api/sim_setup_data/io/siwave.rst

@@ -1,6 +1,6 @@
-Siwave IO
+SIwave IO
 =========
-This class is the container of Siwave IO.
+This class is the container of SIwave IO.
 
 
 .. currentmodule:: pyedb.dotnet.edb_core.sim_setup_data.io.siwave

doc/source/api/utilities/siwave_simulation_setup.rst

@@ -1,4 +1,4 @@
-Siwave simulation setup
+SIwave simulation setup
 =======================
 These classes are the containers of siwave simulation setup.
 

doc/source/user_guide/components/create_rlc_component.rst

@@ -37,4 +37,4 @@ This page shows how to create an RLC component between pins:
 
 .. image:: ../../resources/create_rlc_boundary_on_pin.png
   :width: 800
-  :alt: Create rlc boundary
+  :alt: Create RLC boundary

doc/source/user_guide/edb_information_queries/edb_queries.rst

@@ -8,7 +8,7 @@ these tasks:
 
 - Load a layout.
 - Get statistics.
-- Get nets and plot them in Matplotlib.
+- Get nets and plot them in matplotlib.
 - Get all components and then get pins from components connected to a given net.
 
 .. autosummary::
@@ -40,7 +40,7 @@ Get statistics
    :width: 400
    :alt: Layout stats
 
-Get nets and plot them in Matplotlib
+Get nets and plot them in matplotlib
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
 .. code:: python
@@ -49,12 +49,12 @@ Get nets and plot them in Matplotlib
    edbapp.nets.netlist
    # power nets
    nets.power
-   # Plot nets in Matplotlib
+   # Plot nets in matplotlib
    edbapp.nets.plot(None)
 
 .. image:: ../../resources/layout_plot_all_nets.png
    :width: 800
-   :alt: Plot all nets in Matplotlib
+   :alt: Plot all nets in matplotlib
 
 Get all components and then pins from components connected to a net
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

doc/styles/.gitignore

@@ -1,4 +1,6 @@
 *
-!Vocab
-!Vocab/**
+!config
+!config/vocabularies
+!config/vocabularies/ANSYS
+!config/vocabularies/ANSYS/**
 !.gitignore

doc/styles/Vocab/ANSYS/accept.txt → doc/styles/config/vocabularies/ANSYS/accept.txt

@@ -42,7 +42,7 @@ Q3D
 RaptorX
 RLC
 SimulationConfiguration
-Siwave
+S[Ii]wave
 SYZ
 (?i)stackup(?:\s3D|s)?
 vias

pyproject.toml

@@ -91,8 +91,8 @@ default_section = "THIRDPARTY"
 src_paths = ["doc", "src", "tests"]
 
 [tool.codespell]
-skip = '*.pyc,*.txt,*.gif,*.png,*.jpg,*.js,*.html,*.doctree,*.ttf,*.woff,*.woff2,*.eot,*.mp4,*.inv,*.pickle,*.ipynb,*.a3dcomp,flycheck*,./.git/*,./.hypothesis/*,*.yml,./doc/build/*,./doc/images/*,./dist/*,*~,.hypothesis*,./doc/source/examples/*,*cover,*.dat,*.mac,*.cdb,*.CDB,build,./factory/*,PKG-INFO,*.mypy_cache/*,./_unused/*'
-ignore-words = "doc/styles/Vocab/ANSYS/accept.txt"
+skip = '*.pyc,*.txt,*.gif,*.png,*.jpg,*.js,*.html,*.doctree,*.ttf,*.woff,*.woff2,*.eot,*.mp4,*.inv,*.pickle,*.ipynb,*.a3dcomp,flycheck*,./.git/*,./.hypothesis/*,*.yml,./doc/build/*,./doc/images/*,./dist/*,*~,.hypothesis*,./doc/source/examples/*,*cover,*.dat,*.mac,*.cdb,*.CDB,build,./factory/*,PKG-INFO,*.mypy_cache/*,./_unused/*,pyproject.toml'
+ignore-words = "doc/styles/config/vocabularies/ANSYS/accept.txt"
 ignore-words-list = "renabled, sie, mot"
 enable-colors = true