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Add support for AD9084 Side B FPGA data interfaces #613

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Add tests for new AD9084 side B features
Signed-off-by: Travis F. Collins <travis.collins@analog.com>
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tfcollins committed Nov 1, 2024
commit d3f281733b2a2ab65fe82da4ecb3d18f95b1e810
14 changes: 14 additions & 0 deletions test/emu/hardware_map.yml
Original file line number Diff line number Diff line change
@@ -272,6 +272,20 @@ packrf:
- cf-ad9361-lpc,4
- pyadi_iio_class_support:
- ad9361
adsy1100:
- axi-ad9084-rx-hpc
- axi-ad9084-tx-hpc
- axi-ad9084b-rx-b
- axi-ad9084-tx-b
- pyadi_iio_class_support:
- ad9084
- emulate:
- filename: adsy1100.xml
- data_devices:
- iio:device4
- iio:device5
- iio:device6
- iio:device7

# Generics
ad9361:
25 changes: 25 additions & 0 deletions test/test_ad9084.py
Original file line number Diff line number Diff line change
@@ -304,3 +304,28 @@ def test_ad9084_nco_loopback(


#########################################
@pytest.mark.iio_hardware("adsy1100")
def test_split_rx_buffers(iio_uri):
import adi

dev = adi.ad9084(uri=iio_uri)
dev.rx_buffer_size = 2 ** 10

d = dev.rx()
d1 = dev.rx1()
d2 = dev.rx2()

assert d is not None
assert d1 is not None
assert d2 is not None


#########################################
@pytest.mark.iio_hardware("adsy1100")
@pytest.mark.parametrize("classname", [(classname)])
@pytest.mark.parametrize("channel", [0, 1])
@pytest.mark.parametrize("use_tx2", [False, True])
def test_ad9084_tx_data_split_buffers(
test_dma_tx, iio_uri, classname, channel, use_tx2
):
test_dma_tx(iio_uri, classname, channel, use_tx2)