Add Cache Coherency support on Ultrascale projects

Signed-off-by: Ionut Podgoreanu <[email protected]>
analogdevicesinc · Mar 3, 2025 · fa212ed · fa212ed
1 parent b46731e
commit fa212ed
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Showing 36 changed files with 318 additions and 140 deletions.
diff --git a/projects/ad9081_fmca_ebz/common/ad9081_fmca_ebz_bd.tcl b/projects/ad9081_fmca_ebz/common/ad9081_fmca_ebz_bd.tcl
@@ -1,5 +1,5 @@
 ###############################################################################
-## Copyright (C) 2019-2024 Analog Devices, Inc. All rights reserved.
+## Copyright (C) 2019-2025 Analog Devices, Inc. All rights reserved.
 ### SPDX short identifier: ADIBSD
 ###############################################################################
 
@@ -316,6 +316,7 @@ if {$INTF_CFG != "TX"} {
   } else {
     ad_ip_parameter axi_mxfe_rx_dma CONFIG.DMA_DATA_WIDTH_DEST [expr min(512, $adc_dma_data_width)]
   }
+  ad_ip_parameter axi_mxfe_rx_dma CONFIG.CACHE_COHERENT $CACHE_COHERENCY
 }
 
 # Instantiate DAC (Tx) path
@@ -384,6 +385,7 @@ if {$INTF_CFG != "RX"} {
     ad_ip_parameter axi_mxfe_tx_dma CONFIG.DMA_DATA_WIDTH_SRC [expr min(512, $dac_dma_data_width)]
   }
   ad_ip_parameter axi_mxfe_tx_dma CONFIG.DMA_DATA_WIDTH_DEST $dac_dma_data_width
+  ad_ip_parameter axi_mxfe_tx_dma CONFIG.CACHE_COHERENT $CACHE_COHERENCY
 }
 
 if {$ADI_PHY_SEL == 1} {
@@ -490,8 +492,13 @@ if {$INTF_CFG != "TX"} {
   if {$ADI_PHY_SEL == 1} {
     ad_mem_hp0_interconnect $sys_cpu_clk axi_mxfe_rx_xcvr/m_axi
   }
-  ad_mem_hp1_interconnect $sys_dma_clk sys_ps7/S_AXI_HP1
-  ad_mem_hp1_interconnect $sys_dma_clk axi_mxfe_rx_dma/m_dest_axi
+  if {$CACHE_COHERENCY} {
+    ad_mem_hpc0_interconnect $sys_dma_clk sys_ps8/S_AXI_HPC0
+    ad_mem_hpc0_interconnect $sys_dma_clk axi_mxfe_rx_dma/m_dest_axi
+  } else {
+    ad_mem_hp1_interconnect $sys_dma_clk sys_ps7/S_AXI_HP1
+    ad_mem_hp1_interconnect $sys_dma_clk axi_mxfe_rx_dma/m_dest_axi
+  }
 
   # Interrupts
   ad_cpu_interrupt ps-13 mb-12 axi_mxfe_rx_dma/irq
@@ -541,8 +548,13 @@ if {$INTF_CFG != "RX"} {
   ad_cpu_interconnect 0x7c430000 axi_mxfe_tx_dma
   ad_cpu_interconnect 0x7c440000 $dac_data_offload_name
   # GT / ADC
-  ad_mem_hp2_interconnect $sys_dma_clk sys_ps7/S_AXI_HP2
-  ad_mem_hp2_interconnect $sys_dma_clk axi_mxfe_tx_dma/m_src_axi
+  if {$CACHE_COHERENCY} {
+    ad_mem_hpc1_interconnect $sys_dma_clk sys_ps8/S_AXI_HPC1
+    ad_mem_hpc1_interconnect $sys_dma_clk axi_mxfe_tx_dma/m_src_axi
+  } else {
+    ad_mem_hp2_interconnect $sys_dma_clk sys_ps7/S_AXI_HP2
+    ad_mem_hp2_interconnect $sys_dma_clk axi_mxfe_tx_dma/m_src_axi
+  }
 
   # Interrupts
   ad_cpu_interrupt ps-12 mb-13 axi_mxfe_tx_dma/irq

diff --git a/projects/ad9083_evb/common/ad9083_evb_bd.tcl b/projects/ad9083_evb/common/ad9083_evb_bd.tcl
@@ -1,5 +1,5 @@
 ###############################################################################
-## Copyright (C) 2020-2024 Analog Devices, Inc. All rights reserved.
+## Copyright (C) 2020-2025 Analog Devices, Inc. All rights reserved.
 ### SPDX short identifier: ADIBSD
 ###############################################################################
 
@@ -57,6 +57,7 @@ ad_ip_instance axi_dmac axi_ad9083_rx_dma [list \
   DMA_LENGTH_WIDTH 31 \
   DMA_DATA_WIDTH_DEST 128 \
   DMA_DATA_WIDTH_SRC $adc_dma_data_width \
+  CACHE_COHERENT $CACHE_COHERENCY \
 ]
 
 # common cores
@@ -171,8 +172,13 @@ ad_mem_hp1_interconnect $sys_cpu_clk axi_ad9083_rx_xcvr/m_axi
 
 # interconnect (mem/dac)
 
-ad_mem_hp2_interconnect $sys_dma_clk sys_ps7/S_AXI_HP2
-ad_mem_hp2_interconnect $sys_dma_clk axi_ad9083_rx_dma/m_dest_axi
+if {$CACHE_COHERENCY} {
+  ad_mem_hpc0_interconnect $sys_dma_clk sys_ps8/S_AXI_HPC0
+  ad_mem_hpc0_interconnect $sys_dma_clk axi_ad9083_rx_dma/m_dest_axi
+} else {
+  ad_mem_hp2_interconnect $sys_dma_clk sys_ps7/S_AXI_HP2
+  ad_mem_hp2_interconnect $sys_dma_clk axi_ad9083_rx_dma/m_dest_axi
+}
 
 # interrupts
 

diff --git a/projects/ad9656_fmc/common/ad9656_fmc_bd.tcl b/projects/ad9656_fmc/common/ad9656_fmc_bd.tcl
@@ -48,6 +48,7 @@ ad_ip_instance axi_dmac axi_ad9656_rx_dma [list \
   AXI_SLICE_SRC false \
   DMA_DATA_WIDTH_DEST 128 \
   FIFO_SIZE 32 \
+  CACHE_COHERENT $CACHE_COHERENCY \
   ]
 
 # common cores
@@ -115,8 +116,13 @@ ad_mem_hp0_interconnect $sys_cpu_clk axi_ad9656_rx_xcvr/m_axi
 
 # interconnect (mem/dac)
 
-ad_mem_hp2_interconnect $sys_dma_clk sys_ps7/S_AXI_HP1
-ad_mem_hp2_interconnect $sys_dma_clk axi_ad9656_rx_dma/m_dest_axi
+if {$CACHE_COHERENCY} {
+  ad_mem_hpc0_interconnect $sys_dma_clk sys_ps8/S_AXI_HPC0
+  ad_mem_hpc0_interconnect $sys_dma_clk axi_ad9656_rx_dma/m_dest_axi
+} else {
+  ad_mem_hp2_interconnect $sys_dma_clk sys_ps7/S_AXI_HP2
+  ad_mem_hp2_interconnect $sys_dma_clk axi_ad9656_rx_dma/m_dest_axi
+}
 
 # interrupts
 

diff --git a/projects/ad9694_fmc/common/ad9694_fmc_bd.tcl b/projects/ad9694_fmc/common/ad9694_fmc_bd.tcl
@@ -1,5 +1,5 @@
 ###############################################################################
-## Copyright (C) 2022-2024 Analog Devices, Inc. All rights reserved.
+## Copyright (C) 2022-2025 Analog Devices, Inc. All rights reserved.
 ### SPDX short identifier: ADIBSD
 ###############################################################################
 
@@ -62,6 +62,7 @@ ad_ip_instance axi_dmac axi_ad9694_rx_dma [list \
   DMA_LENGTH_WIDTH 24 \
   DMA_DATA_WIDTH_DEST 128 \
   DMA_DATA_WIDTH_SRC $adc_dma_data_width \
+  CACHE_COHERENT $CACHE_COHERENCY \
   ]
 
 # common cores
@@ -168,8 +169,13 @@ ad_mem_hp0_interconnect $sys_cpu_clk axi_ad9694_rx_xcvr/m_axi
 
 # interconnect (mem/dac)
 
-ad_mem_hp2_interconnect dma_clk_wiz/clk_out1 sys_ps7/S_AXI_HP1
-ad_mem_hp2_interconnect dma_clk_wiz/clk_out1 axi_ad9694_rx_dma/m_dest_axi
+if {$CACHE_COHERENCY} {
+  ad_mem_hpc0_interconnect dma_clk_wiz/clk_out1 sys_ps8/S_AXI_HPC0
+  ad_mem_hpc0_interconnect dma_clk_wiz/clk_out1 axi_ad9694_rx_dma/m_dest_axi
+} else {
+  ad_mem_hp2_interconnect dma_clk_wiz/clk_out1 sys_ps7/S_AXI_HP2
+  ad_mem_hp2_interconnect dma_clk_wiz/clk_out1 axi_ad9694_rx_dma/m_dest_axi
+}
 
 # interrupts
 

diff --git a/projects/ad9695_fmc/common/ad9695_fmc_bd.tcl b/projects/ad9695_fmc/common/ad9695_fmc_bd.tcl
@@ -1,5 +1,5 @@
 ###############################################################################
-## Copyright (C) 2022-2024 Analog Devices, Inc. All rights reserved.
+## Copyright (C) 2022-2025 Analog Devices, Inc. All rights reserved.
 ### SPDX short identifier: ADIBSD
 ###############################################################################
 
@@ -62,6 +62,7 @@ ad_ip_instance axi_dmac axi_ad9695_rx_dma [list \
   DMA_LENGTH_WIDTH 24 \
   DMA_DATA_WIDTH_DEST 128 \
   DMA_DATA_WIDTH_SRC $adc_dma_data_width \
+  CACHE_COHERENT $CACHE_COHERENCY \
   ]
 
 # common cores
@@ -159,8 +160,13 @@ ad_mem_hp0_interconnect $sys_cpu_clk axi_ad9695_rx_xcvr/m_axi
 
 # interconnect (mem/dac)
 
-ad_mem_hp2_interconnect dma_clk_wiz/clk_out1 sys_ps7/S_AXI_HP1
-ad_mem_hp2_interconnect dma_clk_wiz/clk_out1 axi_ad9695_rx_dma/m_dest_axi
+if {$CACHE_COHERENCY} {
+  ad_mem_hpc0_interconnect dma_clk_wiz/clk_out1 sys_ps8/S_AXI_HPC0
+  ad_mem_hpc0_interconnect dma_clk_wiz/clk_out1 axi_ad9695_rx_dma/m_dest_axi
+} else {
+  ad_mem_hp2_interconnect dma_clk_wiz/clk_out1 sys_ps7/S_AXI_HP2
+  ad_mem_hp2_interconnect dma_clk_wiz/clk_out1 axi_ad9695_rx_dma/m_dest_axi
+}
 
 # interrupts
 

diff --git a/projects/ad9783_ebz/common/ad9783_ebz_bd.tcl b/projects/ad9783_ebz/common/ad9783_ebz_bd.tcl
@@ -1,5 +1,5 @@
 ###############################################################################
-## Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved.
+## Copyright (C) 2022-2025 Analog Devices, Inc. All rights reserved.
 ### SPDX short identifier: ADIBSD
 ###############################################################################
 
@@ -27,6 +27,7 @@ ad_ip_parameter axi_ad9783_dma CONFIG.AXI_SLICE_SRC 1
 ad_ip_parameter axi_ad9783_dma CONFIG.DMA_DATA_WIDTH_DEST 128
 ad_ip_parameter axi_ad9783_dma CONFIG.DMA_DATA_WIDTH_SRC 128
 ad_ip_parameter axi_ad9783_dma CONFIG.DMA_AXI_PROTOCOL_SRC 1
+ad_ip_parameter axi_ad9783_dma CONFIG.CACHE_COHERENT $CACHE_COHERENCY
 
 # dac-path channel upack
 
@@ -66,8 +67,13 @@ ad_cpu_interconnect 0x7c420000 axi_ad9783_dma
 
 # interconnect (mem/dac)
 
-ad_mem_hp2_interconnect $sys_dma_clk sys_ps7/S_AXI_HP2
-ad_mem_hp2_interconnect $sys_dma_clk axi_ad9783_dma/m_src_axi
+if {$CACHE_COHERENCY} {
+  ad_mem_hpc0_interconnect $sys_dma_clk sys_ps8/S_AXI_HPC0
+  ad_mem_hpc0_interconnect $sys_dma_clk axi_ad9783_dma/m_src_axi
+} else {
+  ad_mem_hp2_interconnect $sys_dma_clk sys_ps7/S_AXI_HP2
+  ad_mem_hp2_interconnect $sys_dma_clk axi_ad9783_dma/m_src_axi
+}
 ad_connect  $sys_dma_resetn axi_ad9783_dma/m_src_axi_aresetn
 
 # interrupts

diff --git a/projects/adrv9001/common/adrv9001_bd.tcl b/projects/adrv9001/common/adrv9001_bd.tcl
@@ -1,5 +1,5 @@
 ###############################################################################
-## Copyright (C) 2020-2024 Analog Devices, Inc. All rights reserved.
+## Copyright (C) 2020-2025 Analog Devices, Inc. All rights reserved.
 ### SPDX short identifier: ADIBSD
 ###############################################################################
 
@@ -85,6 +85,7 @@ ad_ip_parameter axi_adrv9001_rx1_dma CONFIG.AXI_SLICE_SRC 0
 ad_ip_parameter axi_adrv9001_rx1_dma CONFIG.AXI_SLICE_DEST 0
 ad_ip_parameter axi_adrv9001_rx1_dma CONFIG.DMA_2D_TRANSFER 0
 ad_ip_parameter axi_adrv9001_rx1_dma CONFIG.DMA_DATA_WIDTH_SRC 64
+ad_ip_parameter axi_adrv9001_rx1_dma CONFIG.CACHE_COHERENT $CACHE_COHERENCY
 
 ad_ip_instance util_cpack2 util_adc_1_pack { \
   NUM_OF_CHANNELS 4 \
@@ -102,6 +103,7 @@ ad_ip_parameter axi_adrv9001_rx2_dma CONFIG.AXI_SLICE_SRC 0
 ad_ip_parameter axi_adrv9001_rx2_dma CONFIG.AXI_SLICE_DEST 0
 ad_ip_parameter axi_adrv9001_rx2_dma CONFIG.DMA_2D_TRANSFER 0
 ad_ip_parameter axi_adrv9001_rx2_dma CONFIG.DMA_DATA_WIDTH_SRC 32
+ad_ip_parameter axi_adrv9001_rx2_dma CONFIG.CACHE_COHERENT $CACHE_COHERENCY
 
 ad_ip_instance util_cpack2 util_adc_2_pack { \
   NUM_OF_CHANNELS 2 \
@@ -119,13 +121,14 @@ ad_ip_parameter axi_adrv9001_tx1_dma CONFIG.AXI_SLICE_SRC 0
 ad_ip_parameter axi_adrv9001_tx1_dma CONFIG.AXI_SLICE_DEST 0
 ad_ip_parameter axi_adrv9001_tx1_dma CONFIG.DMA_2D_TRANSFER 0
 ad_ip_parameter axi_adrv9001_tx1_dma CONFIG.DMA_DATA_WIDTH_DEST 64
+ad_ip_parameter axi_adrv9001_tx1_dma CONFIG.CACHE_COHERENT $CACHE_COHERENCY
 
 ad_ip_instance util_upack2 util_dac_1_upack { \
   NUM_OF_CHANNELS 4 \
   SAMPLE_DATA_WIDTH 16 \
 }
 
-# dma for tx1
+# dma for tx2
 
 ad_ip_instance axi_dmac axi_adrv9001_tx2_dma
 ad_ip_parameter axi_adrv9001_tx2_dma CONFIG.DMA_TYPE_SRC 0
@@ -136,6 +139,7 @@ ad_ip_parameter axi_adrv9001_tx2_dma CONFIG.AXI_SLICE_SRC 0
 ad_ip_parameter axi_adrv9001_tx2_dma CONFIG.AXI_SLICE_DEST 0
 ad_ip_parameter axi_adrv9001_tx2_dma CONFIG.DMA_2D_TRANSFER 0
 ad_ip_parameter axi_adrv9001_tx2_dma CONFIG.DMA_DATA_WIDTH_DEST 32
+ad_ip_parameter axi_adrv9001_tx2_dma CONFIG.CACHE_COHERENT $CACHE_COHERENCY
 
 ad_ip_instance util_upack2 util_dac_2_upack { \
   NUM_OF_CHANNELS 2 \
@@ -280,18 +284,27 @@ ad_cpu_interconnect 0x44A40000  axi_adrv9001_rx2_dma
 ad_cpu_interconnect 0x44A50000  axi_adrv9001_tx1_dma
 ad_cpu_interconnect 0x44A60000  axi_adrv9001_tx2_dma
 
-# memory inteconnect
-
-ad_mem_hp1_interconnect $sys_cpu_clk sys_ps7/S_AXI_HP1
-ad_mem_hp1_interconnect $sys_cpu_clk axi_adrv9001_rx1_dma/m_dest_axi
-ad_mem_hp1_interconnect $sys_cpu_clk axi_adrv9001_rx2_dma/m_dest_axi
-ad_mem_hp1_interconnect $sys_cpu_clk axi_adrv9001_tx1_dma/m_src_axi
-ad_mem_hp1_interconnect $sys_cpu_clk axi_adrv9001_tx2_dma/m_src_axi
+# memory interconnect
+
+if {$CACHE_COHERENCY} {
+  ad_mem_hpc0_interconnect $sys_cpu_clk sys_ps8/S_AXI_HPC0
+  ad_mem_hpc0_interconnect $sys_cpu_clk axi_adrv9001_rx1_dma/m_dest_axi
+  ad_mem_hpc0_interconnect $sys_cpu_clk axi_adrv9001_rx2_dma/m_dest_axi
+  ad_mem_hpc0_interconnect $sys_cpu_clk axi_adrv9001_tx1_dma/m_src_axi
+  ad_mem_hpc0_interconnect $sys_cpu_clk axi_adrv9001_tx2_dma/m_src_axi
+} else {
+  ad_mem_hp1_interconnect $sys_cpu_clk sys_ps7/S_AXI_HP1
+  ad_mem_hp1_interconnect $sys_cpu_clk axi_adrv9001_rx1_dma/m_dest_axi
+  ad_mem_hp1_interconnect $sys_cpu_clk axi_adrv9001_rx2_dma/m_dest_axi
+  ad_mem_hp1_interconnect $sys_cpu_clk axi_adrv9001_tx1_dma/m_src_axi
+  ad_mem_hp1_interconnect $sys_cpu_clk axi_adrv9001_tx2_dma/m_src_axi
+}
 
 ad_connect $sys_cpu_resetn axi_adrv9001_rx1_dma/m_dest_axi_aresetn
 ad_connect $sys_cpu_resetn axi_adrv9001_rx2_dma/m_dest_axi_aresetn
 ad_connect $sys_cpu_resetn axi_adrv9001_tx1_dma/m_src_axi_aresetn
 ad_connect $sys_cpu_resetn axi_adrv9001_tx2_dma/m_src_axi_aresetn
+
 # interrupts
 
 ad_cpu_interrupt ps-13 mb-12 axi_adrv9001_rx1_dma/irq

diff --git a/projects/adrv9009/common/adrv9009_bd.tcl b/projects/adrv9009/common/adrv9009_bd.tcl
@@ -1,5 +1,5 @@
 ###############################################################################
-## Copyright (C) 2018-2024 Analog Devices, Inc. All rights reserved.
+## Copyright (C) 2018-2025 Analog Devices, Inc. All rights reserved.
 ### SPDX short identifier: ADIBSD
 ###############################################################################
 
@@ -109,6 +109,7 @@ ad_ip_parameter axi_adrv9009_tx_dma CONFIG.DMA_DATA_WIDTH_DEST $dac_data_width
 ad_ip_parameter axi_adrv9009_tx_dma CONFIG.MAX_BYTES_PER_BURST 256
 ad_ip_parameter axi_adrv9009_tx_dma CONFIG.AXI_SLICE_DEST true
 ad_ip_parameter axi_adrv9009_tx_dma CONFIG.AXI_SLICE_SRC true
+ad_ip_parameter axi_adrv9009_tx_dma CONFIG.CACHE_COHERENT $CACHE_COHERENCY
 
 ad_data_offload_create $dac_offload_name \
                        1 \
@@ -170,6 +171,7 @@ ad_ip_parameter axi_adrv9009_rx_dma CONFIG.DMA_DATA_WIDTH_SRC $adc_dma_data_widt
 ad_ip_parameter axi_adrv9009_rx_dma CONFIG.MAX_BYTES_PER_BURST 256
 ad_ip_parameter axi_adrv9009_rx_dma CONFIG.AXI_SLICE_DEST true
 ad_ip_parameter axi_adrv9009_rx_dma CONFIG.AXI_SLICE_SRC true
+ad_ip_parameter axi_adrv9009_rx_dma CONFIG.CACHE_COHERENT $CACHE_COHERENCY
 
 # adc-os peripherals
 
@@ -215,6 +217,7 @@ ad_ip_parameter axi_adrv9009_rx_os_dma CONFIG.DMA_DATA_WIDTH_SRC [expr $RX_OS_SA
 ad_ip_parameter axi_adrv9009_rx_os_dma CONFIG.MAX_BYTES_PER_BURST 256
 ad_ip_parameter axi_adrv9009_rx_os_dma CONFIG.AXI_SLICE_DEST true
 ad_ip_parameter axi_adrv9009_rx_os_dma CONFIG.AXI_SLICE_SRC true
+ad_ip_parameter axi_adrv9009_rx_os_dma CONFIG.CACHE_COHERENT $CACHE_COHERENCY
 
 # common cores
 
@@ -456,12 +459,20 @@ ad_mem_hp0_interconnect $sys_cpu_clk axi_adrv9009_rx_os_xcvr/m_axi
 
 # interconnect (mem/dac)
 
-ad_mem_hp1_interconnect $sys_dma_clk sys_ps7/S_AXI_HP1
-ad_mem_hp1_interconnect $sys_dma_clk axi_adrv9009_rx_os_dma/m_dest_axi
-ad_mem_hp2_interconnect $sys_dma_clk sys_ps7/S_AXI_HP2
-ad_mem_hp2_interconnect $sys_dma_clk axi_adrv9009_rx_dma/m_dest_axi
-ad_mem_hp3_interconnect $sys_dma_clk sys_ps7/S_AXI_HP3
-ad_mem_hp3_interconnect $sys_dma_clk axi_adrv9009_tx_dma/m_src_axi
+if {$CACHE_COHERENCY} {
+  ad_mem_hpc0_interconnect $sys_dma_clk sys_ps8/S_AXI_HPC0
+  ad_mem_hpc0_interconnect $sys_dma_clk axi_adrv9009_rx_os_dma/m_dest_axi
+  ad_mem_hpc0_interconnect $sys_dma_clk axi_adrv9009_rx_dma/m_dest_axi
+  ad_mem_hpc1_interconnect $sys_dma_clk sys_ps8/S_AXI_HPC1
+  ad_mem_hpc1_interconnect $sys_dma_clk axi_adrv9009_tx_dma/m_src_axi
+} else {
+  ad_mem_hp1_interconnect $sys_dma_clk sys_ps7/S_AXI_HP1
+  ad_mem_hp1_interconnect $sys_dma_clk axi_adrv9009_rx_os_dma/m_dest_axi
+  ad_mem_hp2_interconnect $sys_dma_clk sys_ps7/S_AXI_HP2
+  ad_mem_hp2_interconnect $sys_dma_clk axi_adrv9009_rx_dma/m_dest_axi
+  ad_mem_hp3_interconnect $sys_dma_clk sys_ps7/S_AXI_HP3
+  ad_mem_hp3_interconnect $sys_dma_clk axi_adrv9009_tx_dma/m_src_axi
+}
 
 # interrupts
 

diff --git a/projects/adrv9009zu11eg/common/adrv2crr_fmc_bd.tcl b/projects/adrv9009zu11eg/common/adrv2crr_fmc_bd.tcl
@@ -1,5 +1,5 @@
 ###############################################################################
-## Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved.
+## Copyright (C) 2019-2025 Analog Devices, Inc. All rights reserved.
 ### SPDX short identifier: ADIBSD
 ###############################################################################
 
@@ -95,8 +95,10 @@ ad_cpu_interconnect 0x41000000 i2s_rx_dma
 ad_cpu_interconnect 0x41001000 i2s_tx_dma
 ad_cpu_interconnect 0x42000000 axi_i2s_adi
 
-ad_mem_hp0_interconnect sys_cpu_clk i2s_tx_dma/m_src_axi
-ad_mem_hp0_interconnect sys_cpu_clk i2s_rx_dma/m_dest_axi
+ad_mem_hp1_interconnect sys_cpu_clk sys_ps8/S_AXI_HP1
+ad_mem_hp1_interconnect sys_cpu_clk i2s_tx_dma/m_src_axi
+ad_mem_hp2_interconnect sys_cpu_clk sys_ps8/S_AXI_HP2
+ad_mem_hp2_interconnect sys_cpu_clk i2s_rx_dma/m_dest_axi
 
 # interrupts