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projects/cn0501: Updated with axi_ad7768 IP for Coraz7s
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@PopPaul2021
PopPaul2021 committed Sep 29, 2022
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10 changes: 5 additions & 5 deletions projects/cn0501/Readme.md
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# CN0501 HDL Project

Here are some pointers to help you:
* [Board Product Page](https://www.analog.com/cn0501)
* Parts : []()
* Project Doc:
* HDL Doc:
* Linux Drivers: https://wiki.analog.com/resources/tools-software/linux-drivers-all
* [Board Product Page](https://www.analog.com/en/products/cn0501.html)
* Parts : [CN0501-geophone](https://www.analog.com/en/products/cn0501.html)
* Project Doc: https://wiki.analog.com/resources/eval/user-guides/cn0501
* HDL Doc: https://wiki.analog.com/resources/eval/user-guides/cn0501
* Linux Drivers: https://wiki.analog.com/resources/tools-software/linux-drivers/iio-adc/axi-adc-hdl
158 changes: 46 additions & 112 deletions projects/cn0501/common/cn0501_bd.tcl
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# ad7768 interface

create_bd_port -dir I adc_clk
create_bd_port -dir I adc_valid
create_bd_port -dir I adc_valid_pp
create_bd_port -dir I adc_sync
create_bd_port -dir I -from 31 -to 0 adc_data
create_bd_port -dir I -from 31 -to 0 adc_data_0
create_bd_port -dir I -from 31 -to 0 adc_data_1
create_bd_port -dir I -from 31 -to 0 adc_data_2
create_bd_port -dir I -from 31 -to 0 adc_data_3
create_bd_port -dir I -from 31 -to 0 adc_data_4
create_bd_port -dir I -from 31 -to 0 adc_data_5
create_bd_port -dir I -from 31 -to 0 adc_data_6
create_bd_port -dir I -from 31 -to 0 adc_data_7
create_bd_port -dir I -from 31 -to 0 adc_gpio_0_i
create_bd_port -dir O -from 31 -to 0 adc_gpio_0_o
create_bd_port -dir O -from 31 -to 0 adc_gpio_0_t
create_bd_port -dir I -from 31 -to 0 adc_gpio_1_i
create_bd_port -dir O -from 31 -to 0 adc_gpio_1_o
create_bd_port -dir O -from 31 -to 0 adc_gpio_1_t

create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 iic_0_io

# instances

ad_ip_instance axi_dmac ad7768_dma
ad_ip_parameter ad7768_dma CONFIG.DMA_TYPE_SRC 2
ad_ip_parameter ad7768_dma CONFIG.DMA_TYPE_DEST 0
ad_ip_parameter ad7768_dma CONFIG.CYCLIC 0
ad_ip_parameter ad7768_dma CONFIG.SYNC_TRANSFER_START 1
ad_ip_parameter ad7768_dma CONFIG.AXI_SLICE_SRC 0
ad_ip_parameter ad7768_dma CONFIG.AXI_SLICE_DEST 0
ad_ip_parameter ad7768_dma CONFIG.DMA_2D_TRANSFER 0
ad_ip_parameter ad7768_dma CONFIG.DMA_DATA_WIDTH_SRC 32

ad_ip_instance axi_dmac ad7768_dma_2
ad_ip_parameter ad7768_dma_2 CONFIG.DMA_TYPE_SRC 2
ad_ip_parameter ad7768_dma_2 CONFIG.DMA_TYPE_DEST 0
ad_ip_parameter ad7768_dma_2 CONFIG.CYCLIC 0
ad_ip_parameter ad7768_dma_2 CONFIG.SYNC_TRANSFER_START 1
ad_ip_parameter ad7768_dma_2 CONFIG.AXI_SLICE_SRC 0
ad_ip_parameter ad7768_dma_2 CONFIG.AXI_SLICE_DEST 0
ad_ip_parameter ad7768_dma_2 CONFIG.DMA_2D_TRANSFER 0
ad_ip_parameter ad7768_dma_2 CONFIG.DMA_DATA_WIDTH_SRC 256

# ps7-hp1

ad_ip_parameter sys_ps7 CONFIG.PCW_USE_S_AXI_HP1 1

# gpio

ad_ip_instance axi_gpio ad7768_gpio
ad_ip_parameter ad7768_gpio CONFIG.C_IS_DUAL 1
ad_ip_parameter ad7768_gpio CONFIG.C_GPIO_WIDTH 32
ad_ip_parameter ad7768_gpio CONFIG.C_GPIO2_WIDTH 32
ad_ip_parameter ad7768_gpio CONFIG.C_INTERRUPT_PRESENT 1

#i2c

ad_ip_instance axi_iic axi_iic_0
create_bd_port -dir I clk_in
create_bd_port -dir I ready_in
create_bd_port -dir I -from 7 -to 0 data_in

# adc-path channel pack
# adc(cn0501-dma)

ad_ip_instance util_cpack2 util_ad7768_adc_pack
ad_ip_parameter util_ad7768_adc_pack CONFIG.NUM_OF_CHANNELS 8
ad_ip_parameter util_ad7768_adc_pack CONFIG.SAMPLE_DATA_WIDTH 32
ad_ip_instance axi_dmac cn0501_dma
ad_ip_parameter cn0501_dma CONFIG.DMA_TYPE_SRC 2
ad_ip_parameter cn0501_dma CONFIG.DMA_TYPE_DEST 0
ad_ip_parameter cn0501_dma CONFIG.CYCLIC 0
ad_ip_parameter cn0501_dma CONFIG.SYNC_TRANSFER_START 1
ad_ip_parameter cn0501_dma CONFIG.AXI_SLICE_SRC 0
ad_ip_parameter cn0501_dma CONFIG.AXI_SLICE_DEST 0
ad_ip_parameter cn0501_dma CONFIG.DMA_2D_TRANSFER 0
ad_ip_parameter cn0501_dma CONFIG.DMA_DATA_WIDTH_SRC 256
ad_ip_parameter cn0501_dma CONFIG.DMA_DATA_WIDTH_DEST 64

ad_connect adc_clk util_ad7768_adc_pack/clk
ad_connect sys_rstgen/peripheral_reset util_ad7768_adc_pack/reset
ad_connect adc_valid_pp util_ad7768_adc_pack/fifo_wr_en
# axi_ad77684

for {set i 0} {$i < 8} {incr i} {
ad_connect adc_data_$i util_ad7768_adc_pack/fifo_wr_data_$i
}
ad_ip_instance axi_ad7768 axi_ad7768_adc
ad_ip_parameter axi_ad7768_adc CONFIG.NUM_CHANNELS 8

# adc-path channel pack

# axi_generic_adc
ad_ip_instance util_cpack2 cn0501_adc_pack
ad_ip_parameter cn0501_adc_pack CONFIG.NUM_OF_CHANNELS 8
ad_ip_parameter cn0501_adc_pack CONFIG.SAMPLE_DATA_WIDTH 32

ad_ip_instance axi_generic_adc axi_ad7768_adc
ad_ip_parameter axi_ad7768_adc CONFIG.NUM_OF_CHANNELS 8
# connections

for {set i 0} {$i < 8} {incr i} {
ad_ip_instance xlslice xlslice_$i
set_property -dict [list CONFIG.DIN_FROM $i CONFIG.DIN_WIDTH {8} CONFIG.DOUT_WIDTH {1} CONFIG.DIN_TO $i] [get_bd_cells xlslice_$i]
ad_connect axi_ad7768_adc/adc_enable xlslice_$i/Din
ad_connect xlslice_$i/Dout util_ad7768_adc_pack/enable_$i
ad_connect axi_ad7768_adc/adc_enable_$i cn0501_adc_pack/enable_$i
ad_connect axi_ad7768_adc/adc_data_$i cn0501_adc_pack/fifo_wr_data_$i
}

# interconnects

ad_connect adc_clk ad7768_dma/fifo_wr_clk
ad_connect adc_valid ad7768_dma/fifo_wr_en
ad_connect adc_sync ad7768_dma/fifo_wr_sync
ad_connect adc_data ad7768_dma/fifo_wr_din
ad_connect adc_clk ad7768_dma_2/fifo_wr_clk
ad_connect sys_cpu_resetn ad7768_dma/m_dest_axi_aresetn
ad_connect sys_cpu_resetn ad7768_dma_2/m_dest_axi_aresetn
ad_connect util_ad7768_adc_pack/packed_fifo_wr ad7768_dma_2/fifo_wr
ad_connect util_ad7768_adc_pack/fifo_wr_overflow axi_ad7768_adc/adc_dovf
ad_connect adc_clk axi_ad7768_adc/adc_clk
ad_connect sys_ps7/FCLK_CLK0 axi_ad7768_adc/s_axi_aclk
ad_connect adc_gpio_0_i ad7768_gpio/gpio_io_i
ad_connect adc_gpio_0_o ad7768_gpio/gpio_io_o
ad_connect adc_gpio_0_t ad7768_gpio/gpio_io_t
ad_connect adc_gpio_1_i ad7768_gpio/gpio2_io_i
ad_connect adc_gpio_1_o ad7768_gpio/gpio2_io_o
ad_connect adc_gpio_1_t ad7768_gpio/gpio2_io_t

ad_connect iic_0_io axi_iic_0/iic
ad_connect axi_ad7768_adc/s_axi_aclk sys_ps7/FCLK_CLK0
ad_connect axi_ad7768_adc/clk_in clk_in
ad_connect axi_ad7768_adc/ready_in ready_in
ad_connect axi_ad7768_adc/data_in data_in
ad_connect axi_ad7768_adc/adc_valid cn0501_adc_pack/fifo_wr_en
ad_connect axi_ad7768_adc/adc_clk cn0501_adc_pack/clk
ad_connect axi_ad7768_adc/adc_reset cn0501_adc_pack/reset
ad_connect axi_ad7768_adc/adc_dovf cn0501_adc_pack/fifo_wr_overflow

ad_connect cn0501_dma/s_axi_aclk $sys_cpu_clk
ad_connect cn0501_dma/m_dest_axi_aresetn $sys_cpu_resetn
ad_connect cn0501_dma/m_dest_axi_aclk $sys_cpu_clk
ad_connect cn0501_dma/fifo_wr_clk axi_ad7768_adc/adc_clk
ad_connect cn0501_dma/fifo_wr cn0501_adc_pack/packed_fifo_wr

# interrupts
# cpu / memory interconnects

ad_cpu_interrupt ps-13 mb-13 ad7768_dma/irq
ad_cpu_interrupt ps-12 mb-12 ad7768_gpio/ip2intc_irpt
ad_cpu_interrupt ps-11 mb-11 axi_iic_0/iic2intc_irpt
ad_cpu_interrupt ps-10 mb-10 ad7768_dma_2/irq
ad_cpu_interconnect 0x44a00000 axi_ad7768_adc
ad_cpu_interconnect 0x44a30000 cn0501_dma

# cpu / memory interconnects
ad_mem_hp1_interconnect $sys_cpu_clk sys_ps7/S_AXI_HP1
ad_mem_hp1_interconnect $sys_cpu_clk cn0501_dma/m_dest_axi

ad_cpu_interconnect 0x7C400000 ad7768_dma
ad_cpu_interconnect 0x7C420000 ad7768_gpio
ad_cpu_interconnect 0x7C440000 axi_iic_0
ad_cpu_interconnect 0x7C480000 ad7768_dma_2
ad_cpu_interconnect 0x43c00000 axi_ad7768_adc
# interrupts

ad_mem_hp1_interconnect sys_cpu_clk sys_ps7/S_AXI_HP1
ad_mem_hp0_interconnect sys_cpu_clk ad7768_dma/m_dest_axi
ad_mem_hp1_interconnect sys_cpu_clk ad7768_dma_2/m_dest_axi
ad_cpu_interrupt "ps-13" "mb-13" cn0501_dma/irq
4 changes: 2 additions & 2 deletions projects/cn0501/coraz7s/Makefile
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Expand Up @@ -11,10 +11,10 @@ M_DEPS += ../../scripts/adi_pd.tcl
M_DEPS += ../../common/coraz7s/coraz7s_system_ps7.tcl
M_DEPS += ../../common/coraz7s/coraz7s_system_constr.xdc
M_DEPS += ../../common/coraz7s/coraz7s_system_bd.tcl
M_DEPS += ../../ad7768evb/common/ad7768_if.v
M_DEPS += ../../../library/common/ad_iobuf.v

LIB_DEPS += axi_ad7768
LIB_DEPS += axi_dmac
LIB_DEPS += axi_generic_adc
LIB_DEPS += axi_sysid
LIB_DEPS += sysid_rom
LIB_DEPS += util_pack/util_cpack2
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7 changes: 2 additions & 5 deletions projects/cn0501/coraz7s/system_bd.tcl
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source $ad_hdl_dir/projects/common/coraz7s/coraz7s_system_bd.tcl
source ../common/cn0501_bd.tcl
source $ad_hdl_dir/projects/scripts/adi_pd.tcl

#system ID
ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9
ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "[pwd]/mem_init_sys.txt"
ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9
set sys_cstring "sys rom custom string placeholder"
sysid_gen_sys_init_file $sys_cstring

#set sys_dma_clk [get_bd_nets sys_dma_clk]

source ../common/cn0501_bd.tcl
sysid_gen_sys_init_file $sys_cstring
41 changes: 22 additions & 19 deletions projects/cn0501/coraz7s/system_constr.xdc
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set_property -dict {PACKAGE_PIN N18 IOSTANDARD LVCMOS33} [get_ports clk_in ]; ## P12.10 IO8
set_property -dict {PACKAGE_PIN M18 IOSTANDARD LVCMOS33} [get_ports ready_in ]; ## P12.9 IO9

set_property -dict {PACKAGE_PIN U14 IOSTANDARD LVCMOS33} [get_ports data_in[7]]; ## P14.1 IO0
set_property -dict {PACKAGE_PIN V13 IOSTANDARD LVCMOS33} [get_ports data_in[6]]; ## P14.2 IO1
set_property -dict {PACKAGE_PIN T14 IOSTANDARD LVCMOS33} [get_ports data_in[5]]; ## P14.3 IO2
set_property -dict {PACKAGE_PIN T15 IOSTANDARD LVCMOS33} [get_ports data_in[4]]; ## P14.4 IO3
set_property -dict {PACKAGE_PIN V17 IOSTANDARD LVCMOS33} [get_ports data_in[3]]; ## P14.1 IO4
set_property -dict {PACKAGE_PIN V18 IOSTANDARD LVCMOS33} [get_ports data_in[2]]; ## P14.2 IO5
set_property -dict {PACKAGE_PIN R17 IOSTANDARD LVCMOS33} [get_ports data_in[1]]; ## P14.3 IO6
set_property -dict {PACKAGE_PIN R14 IOSTANDARD LVCMOS33} [get_ports data_in[0]]; ## P14.4 IO7

set_property -dict {PACKAGE_PIN U15 IOSTANDARD LVCMOS33} [get_ports spi_csn ]; ## P12.8 IO10
set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVCMOS33} [get_ports spi_mosi ]; ## P12.7 IO11
set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVCMOS33} [get_ports spi_miso ]; ## P12.6 IO12
set_property -dict {PACKAGE_PIN G15 IOSTANDARD LVCMOS33} [get_ports spi_clk ]; ## P12.5 IO13

set_property -dict {PACKAGE_PIN N18 IOSTANDARD LVCMOS33} [get_ports clk_in] ; ## IO8
set_property -dict {PACKAGE_PIN M18 IOSTANDARD LVCMOS33} [get_ports ready_in] ; ## IO9
set input_clock_period 31.25; # Period of input clock fMAX_DCLK=32MHz
set hold_time 8.5;
set setup_time 8.5;

set_property -dict {PACKAGE_PIN R14 IOSTANDARD LVCMOS33} [get_ports data_in[0]] ; ## IO7
set_property -dict {PACKAGE_PIN R17 IOSTANDARD LVCMOS33} [get_ports data_in[1]] ; ## IO6
set_property -dict {PACKAGE_PIN V18 IOSTANDARD LVCMOS33} [get_ports data_in[2]] ; ## IO5
set_property -dict {PACKAGE_PIN V17 IOSTANDARD LVCMOS33} [get_ports data_in[3]] ; ## IO4
set_property -dict {PACKAGE_PIN T15 IOSTANDARD LVCMOS33} [get_ports data_in[4]] ; ## IO3
set_property -dict {PACKAGE_PIN T14 IOSTANDARD LVCMOS33} [get_ports data_in[5]] ; ## IO2
set_property -dict {PACKAGE_PIN V13 IOSTANDARD LVCMOS33} [get_ports data_in[6]] ; ## IO1
set_property -dict {PACKAGE_PIN U14 IOSTANDARD LVCMOS33} [get_ports data_in[7]] ; ## IO0
create_clock -name adc_clk -period $input_clock_period [get_ports clk_in]

set_property -dict {PACKAGE_PIN U15 IOSTANDARD LVCMOS33} [get_ports spi_csn] ; ## IO10
set_property -dict {PACKAGE_PIN G15 IOSTANDARD LVCMOS33} [get_ports spi_clk] ; ## IO13
set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVCMOS33} [get_ports spi_mosi] ; ## IO11
set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVCMOS33} [get_ports spi_miso] ; ## IO12

set_property -dict {PACKAGE_PIN P16 IOSTANDARD LVCMOS33} [get_ports iic_scl]
set_property -dict {PACKAGE_PIN P15 IOSTANDARD LVCMOS33} [get_ports iic_sda]

create_clock -name adc_clk -period 20 [get_ports clk_in]
set_input_delay -clock adc_clk -max [expr $input_clock_period - $setup_time] [get_ports data_in[*]] -clock_fall -add_delay;
set_input_delay -clock adc_clk -min $hold_time [get_ports data_in[*]] -clock_fall -add_delay;
13 changes: 6 additions & 7 deletions projects/cn0501/coraz7s/system_project.tcl
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# load script
source ../../../scripts/adi_env.tcl
source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl
source $ad_hdl_dir/projects/scripts/adi_board.tcl

adi_project cn0501_coraz7s

adi_project_files cn0501_coraz7s [list \
"$ad_hdl_dir/projects/ad7768evb/common/ad7768_if.v" \
"$ad_hdl_dir/projects/common/coraz7s/coraz7s_system_constr.xdc" \
"system_top.v" \
"system_constr.xdc" \
]

"$ad_hdl_dir/projects/common/coraz7s/coraz7s_system_constr.xdc" \
"$ad_hdl_dir/library/common/ad_iobuf.v" \
"system_top.v" \
"system_constr.xdc" ]

adi_project_run cn0501_coraz7s
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