This project presents an Advanced Encryption Standard (AES) core implemented in Verilog. The AES core provides a hardware-accelerated solution for encrypting and decrypting data using the AES algorithm. AES is a widely adopted symmetric encryption algorithm, offering a high level of security and efficiency.
AES Implementation: The core is designed to support AES encryption and decryption operations based on the AES algorithm specifications. It provides a streamlined and optimized hardware implementation for efficient processing of data.
Configurable Key Size: The AES core supports multiple key sizes, including 128-bit, 192-bit, and 256-bit, allowing flexibility in selecting the desired level of security.