Skip to content

Fix post-synthesis simulation in yosys #5

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Open
wants to merge 2 commits into
base: master
Choose a base branch
from
Open

Fix post-synthesis simulation in yosys #5

Changes from all commits
Commits
Show all changes
2 commits
Select commit Hold shift + click to select a range
752e924
Remove unused variable
Forty-Bot Jan 2, 2023
2ae88c6
Fix assignment of state_val/data_val
Forty-Bot Jan 2, 2023
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
10 changes: 5 additions & 5 deletions rtl/lfsr.v
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -201,10 +201,10 @@ reg [DATA_WIDTH-1:0] lfsr_mask_data[LFSR_WIDTH-1:0];
reg [LFSR_WIDTH-1:0] output_mask_state[DATA_WIDTH-1:0];
reg [DATA_WIDTH-1:0] output_mask_data[DATA_WIDTH-1:0];

reg [LFSR_WIDTH-1:0] state_val = 0;
reg [DATA_WIDTH-1:0] data_val = 0;
reg [LFSR_WIDTH-1:0] state_val;
reg [DATA_WIDTH-1:0] data_val;

integer i, j, k;
integer i, j;

initial begin
// init bit masks
Expand Down Expand Up @@ -391,8 +391,8 @@ end else if (STYLE_INT == "LOOP") begin
// same size as generated code with Quartus
// --> better for synthesis

reg [LFSR_WIDTH-1:0] state_out_reg = 0;
reg [DATA_WIDTH-1:0] data_out_reg = 0;
reg [LFSR_WIDTH-1:0] state_out_reg;
reg [DATA_WIDTH-1:0] data_out_reg;

assign state_out = state_out_reg;
assign data_out = data_out_reg;
Expand Down