aklofas · TeinkBR · Jul 30, 2026 · Jul 30, 2026
diff --git a/.agents/skills/clock-tree b/.agents/skills/clock-tree
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+../../skills/clock-tree
diff --git a/.agents/skills/constraint-management b/.agents/skills/constraint-management
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+../../skills/constraint-management
diff --git a/.agents/skills/design-review b/.agents/skills/design-review
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+../../skills/design-review
diff --git a/.agents/skills/dfm-review b/.agents/skills/dfm-review
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+../../skills/dfm-review
diff --git a/.agents/skills/eda-prompt-engineering b/.agents/skills/eda-prompt-engineering
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+../../skills/eda-prompt-engineering
diff --git a/.agents/skills/hw-architecture-review b/.agents/skills/hw-architecture-review
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+../../skills/hw-architecture-review
diff --git a/.agents/skills/knowledge-management b/.agents/skills/knowledge-management
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+../../skills/knowledge-management
diff --git a/.agents/skills/multi-agent-coordination b/.agents/skills/multi-agent-coordination
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+../../skills/multi-agent-coordination
diff --git a/.agents/skills/pcb-layout-review b/.agents/skills/pcb-layout-review
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+../../skills/pcb-layout-review
diff --git a/.agents/skills/power-tree b/.agents/skills/power-tree
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+../../skills/power-tree
diff --git a/.agents/skills/product-docs b/.agents/skills/product-docs
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+../../skills/product-docs
diff --git a/.agents/skills/schematic-presentation b/.agents/skills/schematic-presentation
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+../../skills/schematic-presentation
diff --git a/.agents/skills/si-review b/.agents/skills/si-review
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+../../skills/si-review
diff --git a/.agents/skills/verification-planning b/.agents/skills/verification-planning
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+../../skills/verification-planning
diff --git a/CHANGELOG.md b/CHANGELOG.md
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+## Unreleased — workflow intelligence skills
+
+### Added
+- Methodology skills for architecture, layout review, power/clock trees, constraint/SoT management, DFM/SI signoff, design-review charters, verification planning, schematic presentation, product docs, and agent ops (prompting, multi-agent, knowledge management)
+- `kidoc` engineering documentation skill
+- Cross-links from core `kicad` Related Skills table
+
+### Changed
+- `llms.txt` / README discoverability for methodology skills
+- Default remotes on TeinkBR fork: `origin` → TeinkBR, `upstream` → aklofas
+
 # Changelog
 
 All notable changes to kicad-happy are documented here.

diff --git a/README.md b/README.md
@@ -420,6 +420,28 @@ Or set up the [GitHub Action](github-action.md) and get automated analysis on ev
 
 **Optional Python packages**: `requests` (better HTTP), `playwright` (JS-heavy datasheet sites), `pdftotext` (PDF text extraction).
 
+
+## Workflow Intelligence (methodology)
+
+These skills teach **review and ops methodology**. They hand off to `kicad` / `emc` / `jlcpcb` analyzers rather than duplicating parsers.
+
+| Skill | Purpose |
+|-------|---------|
+| [hw-architecture-review](skills/hw-architecture-review/SKILL.md) | System topology, interface ownership, dual-SoT |
+| [pcb-layout-review](skills/pcb-layout-review/SKILL.md) | Layout critique & ECO classes |
+| [power-tree](skills/power-tree/SKILL.md) / [clock-tree](skills/clock-tree/SKILL.md) | Power & clock domain reviews |
+| [constraint-management](skills/constraint-management/SKILL.md) | Freeze, SoT, write gates |
+| [dfm-review](skills/dfm-review/SKILL.md) / [si-review](skills/si-review/SKILL.md) | Fab GO & tiered SI |
+| [design-review](skills/design-review/SKILL.md) | Chartered reviews, honest score ceilings |
+| [schematic-presentation](skills/schematic-presentation/SKILL.md) | Industrial drawing polish |
+| [product-docs](skills/product-docs/SKILL.md) | Commercial / CEM documentation |
+| [verification-planning](skills/verification-planning/SKILL.md) | Lab & bring-up plans |
+| [eda-prompt-engineering](skills/eda-prompt-engineering/SKILL.md) | Grounded agent prompts |
+| [multi-agent-coordination](skills/multi-agent-coordination/SKILL.md) | Overnight / parallel HW agents |
+| [knowledge-management](skills/knowledge-management/SKILL.md) | Journals, scorecards, indexes |
+| [kidoc](skills/kidoc/SKILL.md) | Generate HDD/ICD/CE/manufacturing docs from CAD |
+
+
 ## ✅ KiCad version support
 
 | Version  | Schematic                     | PCB  | Gerber |

diff --git a/llms.txt b/llms.txt
@@ -2,7 +2,7 @@
 
 > AI-powered design review skills for KiCad electronics projects
 
-A suite of 11 skills that turn an AI coding agent into an electronics design assistant. Structured Python analysis scripts (zero dependencies, Python 3.10+ stdlib only) for KiCad 5-10 projects. Works with Claude Code, OpenAI Codex, Cursor, and Gemini CLI.
+A suite of 25+ skills that turn an AI coding agent into an electronics design assistant. Structured Python analysis scripts (zero dependencies, Python 3.10+ stdlib only) for KiCad 5-10 projects. Works with Claude Code, OpenAI Codex, Cursor, and Gemini CLI.
 
 Capabilities: schematic analysis (40+ subcircuit detectors), PCB layout review, EMC pre-compliance (44 rules), SPICE simulation, thermal analysis, component sourcing (DigiKey/Mouser/LCSC/element14), BOM management, manufacturing prep (JLCPCB/PCBWay), and professional documentation generation.
 
@@ -33,3 +33,17 @@ Install: `/plugin marketplace add aklofas/kicad-happy` (Claude Code), `gemini sk
 
 - [JLCPCB](https://github.com/aklofas/kicad-happy/blob/main/skills/jlcpcb/SKILL.md): BOM/CPL format, assembly constraints, basic vs extended parts
 - [PCBWay](https://github.com/aklofas/kicad-happy/blob/main/skills/pcbway/SKILL.md): Turnkey assembly rules, MPN-based sourcing
+
+
+## Workflow Intelligence Skills (methodology)
+
+- [Hardware Architecture Review](skills/hw-architecture-review/SKILL.md): Topology, ownership, dual-SoT, commercial reference match
+- [PCB Layout Review](skills/pcb-layout-review/SKILL.md): Placement/stackup/ECO classes beyond analyzer JSON
+- [Power Tree](skills/power-tree/SKILL.md) / [Clock Tree](skills/clock-tree/SKILL.md): Rail and REFCLK methodology
+- [Constraint Management](skills/constraint-management/SKILL.md): Copper freeze, SoT, agent write gates
+- [DFM Review](skills/dfm-review/SKILL.md) / [SI Review](skills/si-review/SKILL.md): Fab GO gate and tiered SI signoff
+- [Design Review](skills/design-review/SKILL.md): Chartered reviews and honest EQ ceilings
+- [Schematic Presentation](skills/schematic-presentation/SKILL.md) / [Product Docs](skills/product-docs/SKILL.md): Drawing polish and commercial manuals
+- [Verification Planning](skills/verification-planning/SKILL.md): Lab and bring-up gates
+- [EDA Prompt Engineering](skills/eda-prompt-engineering/SKILL.md) / [Multi-Agent Coordination](skills/multi-agent-coordination/SKILL.md) / [Knowledge Management](skills/knowledge-management/SKILL.md): Agent ops
+- [kidoc](skills/kidoc/SKILL.md): Engineering documentation generation from CAD
diff --git a/skills/clock-tree/SKILL.md b/skills/clock-tree/SKILL.md
@@ -0,0 +1,101 @@
+---
+name: clock-tree
+description: >-
+  Review clock and REFCLK trees: oscillator choice, HCSL/LVDS/CMOS distribution,
+  AC-coupling, series termination, fanout, SSC, and multi-load PCIe clocking. Use
+  for REFCLK reviews, crystal load-cap checks, clock domain maps, or "who drives
+  the clock" disputes on PCIe/FPGA/embedded boards.
+---
+
+# Clock Tree Review
+
+## Related Skills
+
+| Skill | Role |
+|-------|------|
+| `kicad` | Crystal / oscillator detectors, load-cap checks |
+| `si-review` | Length, impedance, coupling of clock traces |
+| `emc` | Clock harmonic / edge radiation rules |
+| `hw-architecture-review` | Clock ownership in system architecture |
+| `verification-planning` | Scope REFCLK bring-up |
+| `datasheets` | Oscillator / buffer integration rules |
+
+## Purpose
+
+Map every clock source → buffer/fanout → loads with electrical standard,
+termination, and verification method. Separate **architectural correctness**
+from **jitter compliance** (lab-only).
+
+## When to invoke
+
+- PCIe REFCLK ownership debates (host vs onboard XO vs clock gen)
+- Dual-slot / dual-load clocking
+- Crystal load-cap validation
+- Before claiming link-ready in EQ scorecards
+
+## Inputs
+
+- Schematic SoT + `analyze_schematic.py` JSON
+- Architecture clocking decision (common clock / SRNS / SRIS)
+- Oscillator and receiver datasheets (or `datasheets` cache)
+- PCB lengths for clock nets (optional `analyze_pcb`)
+
+## Outputs
+
+1. Clock tree diagram (text)
+2. Load table: source, format, termination, sheet refs
+3. Risk list → verification IDs
+4. Non-claims (jitter, SSC legality, Gen timing)
+
+## Decision process
+
+1. Inventory oscillators, crystals, clock gens, FPGA/SoC clock pins.
+2. Classify: local XTAL, distributed REFCLK, recovered clock, PLL cascade.
+3. For PCIe REFCLK: common clock vs SRNS/SRIS; who sources; series-R / AC-cap policy.
+4. Fanout: single load vs dual-slot; buffer needed?
+5. Spread-spectrum: intentional or forbidden for the link class.
+6. EMC: edge rate and harmonic risk → `emc`.
+7. Lab: probe points; do not claim compliance from schematic.
+
+### Correct vs anti-pattern
+
+| Correct | Anti-pattern |
+|---------|--------------|
+| Document Option A onboard XO + series R | Swap host/onboard clocks silently |
+| Dual-load flagged for scope | Assume HCSL drives N loads forever |
+| MEASURE amplitude/duty | EQ credit for “looks terminated” |
+
+## Checklist
+
+- [ ] Source and format (HCSL/LVDS/CMOS/LVPECL) stated
+- [ ] Each load listed with termination
+- [ ] Coupling caps / series R refs documented
+- [ ] Unused clock pins handled (PD/PU/NC per datasheet)
+- [ ] Crystal CL / load caps checked (analyzer + datasheet)
+- [ ] Dual-load or long stubs flagged
+- [ ] MEASURE items for amplitude / duty / jitter
+
+## Failure modes
+
+| Mode | Root cause | Impact | Improvement |
+|------|------------|--------|-------------|
+| Host vs onboard ambiguity | Spec skim | Enum fail | Ownership table |
+| Missing AC-coupling | Pattern copy error | Link flaky | Datasheet gate |
+| Fake Gen timing claim | Score pressure | Misleading GO | Non-claims |
+
+## Industrial references
+
+- PCIe Base Spec clocking chapters (cite revision)
+- HCSL buffer vendor app notes
+- JLCPCB guide: group clock circuitry on dedicated schematic pages
+- pcbGPT semantic failures often omit support passives on clock/power pins
+
+## Example
+
+**MatriQ-like:** Onboard Y1 HCSL REFCLK to RC and EP connectors with series resistors R20/R21 policy documented; dual-load → Phase 7-D scope gate; no jitter EQ points until measured.
+
+## Acceptance criteria
+
+- Clock tree diagram + load table delivered
+- Explicit non-claim on jitter compliance without measurement
+- Handoff IDs created in verification-planning when dual-load or long routes exist
diff --git a/skills/constraint-management/SKILL.md b/skills/constraint-management/SKILL.md
@@ -0,0 +1,79 @@
+---
+name: constraint-management
+description: >-
+  Manage hardware design constraints and sources of truth: copper freeze, dual
+  schematic SoT, UUID/file affinity, net classes, design rules, and write-gate
+  policies for AI agents. Use when locking fab packages, resolving SoT conflicts,
+  session guardian / CAD trust, "do not edit copper", hierarchy Sheetfile policy,
+  or constraint-guided agent workflows.
+---
+
+# Constraint & SoT Management
+
+Implements the industrial lesson: **automation is constrained optimization**
+(Quilter; PCBWorld engine feedback; PCBSchemaGen constraint-guided synthesis).
+
+## Related Skills
+
+| Skill | Role |
+|-------|------|
+| `kicad` | Read net classes, rules, board metadata |
+| `pcb-layout-review` | Apply fab rules in layout critique |
+| `dfm-review` | Map constraints to fab capability |
+| `multi-agent-coordination` | Enforce write gates across agents |
+| `design-review` | Score honesty when constraints block EQ |
+
+## Purpose
+
+Maintain a written constraint set that agents and humans must obey: what file is
+SoT, what may be edited, what invalidates fab GO.
+
+## Constraint categories
+
+1. **File SoT** — PCB path; customer sch; archival sch
+2. **Edit class** — docs / presentation / copper / hierarchy pins
+3. **Electrical rules** — clearance, width, diff pair, via
+4. **Process** — fab stackup, finish, min drill
+5. **Trust** — LIVE GUI must match CLI file (UUID affinity)
+6. **Claims** — what EQ/compliance language is forbidden without evidence
+
+## Decision process
+
+1. Publish a constraint card at campaign start (markdown table).
+2. On every edit request: classify impact → allowed?
+3. Copper freeze after fab GO until evidence demands ECO.
+4. Dual-SoT: name roles; ban false ERC proofs.
+5. Prefer engine/API edits over regex sexp rewrites.
+6. Log constraint waivers with owner + expiry.
+
+## Checklist
+
+- [ ] PCB SoT path absolute or repo-relative, single
+- [ ] Schematic customer SoT vs archival named
+- [ ] Copper freeze flag + CAM zip hash/name
+- [ ] Net classes exist for HS / power / default
+- [ ] Fab rules imported or cited
+- [ ] Agent write mode + profile documented
+- [ ] LIVE==CLI procedure defined
+- [ ] Waiver log location defined
+
+## Failure modes
+
+| Mode | MatriQ lesson |
+|------|---------------|
+| Hollow hier ERC=0 as proof | Dual-SoT policy required |
+| Sibling Sheetfile surprise ERC | Experiment with revert path |
+| Score chasing copper ECO | Freeze + lab-first EQ>95 |
+| Regex CAD edits | Ban; use MCP/API |
+
+## Industrial references
+
+- PCBWorld engine-grounded DRC loop (arXiv:2607.05915)
+- PCBSchemaGen constraint-guided synthesis + KG verifier (arXiv:2602.00510)
+- Quilter constrained-optimization framing
+- Agentic EDA handoff contracts (arXiv:2606.19795)
+
+## Acceptance criteria
+
+- Constraint card exists and is cited by agents before edits
+- Fab-invalidating actions require explicit human unlock language
diff --git a/skills/constraint-management/references/constraint-card-template.md b/skills/constraint-management/references/constraint-card-template.md
@@ -0,0 +1,11 @@
+# Constraint card template
+
+| ID | Constraint | Value | Owner | Unlocks |
+|----|------------|-------|-------|---------|
+| C-PCB | PCB SoT | `board_4layer.kicad_pcb` | HW lead | — |
+| C-SCH-CUST | Customer sch | `sheets/00_….kicad_sch` | HW lead | — |
+| C-SCH-ARCH | Archival sch | `flat.kicad_sch` | HW lead | — |
+| C-CU | Copper freeze | ON after fab GO | HW lead | Evidence ECO |
+| C-FAB | CAM package | `…_uncond_go.zip` | MFG | Re-export |
+| C-WRITE | Agent write | MCP write / API only | Tools | — |
+| C-CLAIM | EQ>95 | Needs lab SI + silicon | Lead | MEASURE |
diff --git a/skills/design-review/SKILL.md b/skills/design-review/SKILL.md
@@ -0,0 +1,75 @@
+---
+name: design-review
+description: >-
+  Design review methodology and charters: evidence-backed findings, EQ
+  scorecards, severity classes, verification basis, false-positive triage, and
+  honest ceilings. Use for formal design reviews, principal reviews, scorecard
+  updates, or "ready for fab" verdicts that must not invent lab scores.
+---
+
+# Design Review Methodology
+
+Orchestrates other skills into a **chartered** review. Extends the `kicad` Design
+Review Contract with industrial scoring honesty (MatriQ EQ lessons).
+
+## Related Skills
+
+| Skill | When |
+|-------|------|
+| `kicad` + `emc` + `spice` | Analyzer evidence |
+| `hw-architecture-review` | Topology |
+| `pcb-layout-review` / `dfm-review` / `si-review` | Domain chapters |
+| `verification-planning` | Residual gates |
+| `multi-agent-coordination` | Parallel reviewers |
+| `kidoc` | Design review package export |
+
+## Purpose
+
+Ship a review that a principal engineer trusts: verdict, blockers, skipped
+analyses, verification basis, and score **ceilings**.
+
+## Review charter (minimum)
+
+1. Scope + SoT files
+2. Required analyzers list (run or explicit skip)
+3. Severity model (blocker / major / minor / note)
+4. Verification basis labels (analyzer / datasheet / lab / conjecture)
+5. False-positive triage step
+6. EQ or readiness score with formula + forbidden claims
+
+## Decision process
+
+1. Read charter; refuse uncoped “looks good”.
+2. Gather analyzer evidence; triage FPs.
+3. Domain chapters via specialized skills.
+4. Score only dimensions with evidence; cap SI/PI/compliance without lab.
+5. Separate docs/process Δ from physical Δ.
+6. Verdict: GO / CONDITIONAL / NO-GO + next human actions (≤3).
+
+## Checklist
+
+- [ ] SoT + LIVE==CLI
+- [ ] Analyzer matrix completed
+- [ ] Blockers table
+- [ ] Skipped analyses disclosed
+- [ ] FP triage notes
+- [ ] Score ceiling rationale
+- [ ] Fab GO impact explicit
+
+## Failure modes
+
+- Stopping after schematic+PCB JSON dump
+- Claiming verified without datasheet
+- EQ>95 from overnight cosmetics (MatriQ blocked by SI+silicon)
+- Agent timeout residue scored as progress
+
+## Industrial references
+
+- kicad-happy Design Review Contract
+- pcbGPT: expert review still required (pass@1 hard tasks 0.72)
+- Agentic EDA handoff validity (arXiv:2606.19795)
+
+## Acceptance criteria
+
+- Principal can sign from the package
+- Physical vs docs deltas separated