[AArch64] Update disassembler based on 2025-06 ARM ISA data

[bdash]

Alongside the update I also added support for decoding:

• LDR / STR (table)
• PMULLB / PMULLT
• ABS / CNT / CTZ
• SMIN / SMAX / UMIN / UMAX
• RPRFM
• PSEL

Note that while these instructions will now be disassembled, they are not yet lifted to LLIL.

Additionally, I fixed a number of errors in the decoding of some less commonly occurring instructions.

Fixes #7402.

[plafosse]

Just marking down my observations:
Removing sysreg.h - I assume this is due to how we're handling these as enums now, and this is no longer needed?
You fixed FPOne and FPTwo - Surprised that code wasn't throwing a warning....
New register REG_ZT0?
Looks like sysregs_gen.h has not been updated was this intentional?
Looks like there are ~500 more instruction in operations.h were we really missing that many?

[bdash]

The large number of new operations is due to many features being picked up for the first time. And many of the new instructions have multiple variants.

• FEAT_LSFE, FEAT_LSE128, and FEAT_LSUI add new atomic operations with multiple variants for the different combinations of acquire / release semantics. These account for between half and two thirds of the new instructions.
• FEAT_MOPS adds 40 different memory set / memory copy instructions that each have 3 variants.
• FEAT_CMPBR adds 36 different comparison instructions (6 base instructions with 6 different condition codes).
• FEAT_THE adds 12 instructions related to TLB handling that each have 4 variants.
• FEAT_CSSC adds 22 new instructions.

The code related to sysregs was changed to be generated in b095215 but the old version of the code was not removed.

ZT0 is added as part of FEAT_SME2.