VHDL · Paebbels · Oct 13, 2025 · Oct 13, 2025 · Oct 13, 2025 · Oct 13, 2025
diff --git a/.github/workflows/Pipeline.yml b/.github/workflows/Pipeline.yml
@@ -18,7 +18,7 @@ jobs:
       matrix:
         include:
           - { simulator: 'nvc',  backend: '',      version: 'latest', can-fail: false }
-          - { simulator: 'ghdl', backend: 'mcode', version: 'latest', can-fail: false }
+#          - { simulator: 'ghdl', backend: 'mcode', version: 'latest', can-fail: false }
           - { simulator: 'ghdl', backend: 'llvm',  version: 'latest', can-fail: false }
     with:
       simulator:    ${{ matrix.simulator }}
@@ -123,7 +123,7 @@ jobs:
       contents: write  # required for create tag
       actions:  write  # required for trigger workflow
     with:
-      version:  ${{ needs.Prepare.output.version }}
+      version:  ${{ needs.Prepare.outputs.version }}
       auto_tag: ${{ needs.Prepare.outputs.is_release_commit }}
 
   Release:

diff --git a/.github/workflows/Simulate.yml b/.github/workflows/Simulate.yml
@@ -110,7 +110,7 @@ jobs:
     continue-on-error: ${{ inputs.can-fail }}
     steps:
       - name: ⏬ Checkout repository
-        uses: actions/checkout@v4
+        uses: actions/checkout@v6
         with:
           lfs: true
           submodules: true
@@ -216,7 +216,7 @@ jobs:
     continue-on-error: ${{ inputs.can-fail }}
     steps:
       - name: ⏬ Checkout repository
-        uses: actions/checkout@v4
+        uses: actions/checkout@v6
         with:
           lfs: true
           submodules: true
@@ -307,9 +307,11 @@ jobs:
           }
 
           if {$::osvvm::ToolName eq "GHDL"} {
+            SetExtendedAnalyzeOptions  {-frelaxed -Wno-specs -Wno-elaboration}
             SetExtendedSimulateOptions {-frelaxed -Wno-specs -Wno-binding}
           }
           if {$::osvvm::ToolName eq "NVC"} {
+            SetExtendedAnalyzeOptions {--relaxed}
           }
 
           build ../../tb/RunAllTests.pro

diff --git a/.gitignore b/.gitignore
@@ -39,6 +39,9 @@ tb/common/my_project.vhdl
 
 
 # ignore external tool files: ActiveHDL, QuestaSim
+/.sigasi/**/
+!/.sigasi/project.sigasi
+
 /prj/ActiveHDL/*
 /prj/ActiveHDL/*.*
 /prj/ActiveHDL/**/*.*

diff --git a/README.md b/README.md
@@ -5,8 +5,8 @@
 [![Sourcecode License](https://img.shields.io/badge/code-Apache%202.0-97CA00?longCache=true&style=flat-square&longCache=true&logo=Apache)](LICENSE.md)
 [![Documentation](https://img.shields.io/website?longCache=true&style=flat-square&label=VHDL.github.io%2FPoC&logo=GitHub&logoColor=fff&up_color=blueviolet&up_message=Read%20now%20%E2%9E%9A&url=https%3A%2F%2FVHDL.github.io%2FPoC%2Findex.html)](https://VHDL.github.io/PoC/)
 [![Documentation License](https://img.shields.io/badge/doc-CC--BY%204.0-green?longCache=true&style=flat-square&logo=CreativeCommons&logoColor=fff)](docs/Doc-License.rst)    
-![Latest tag](https://img.shields.io/github/tag/VLSI-EDA/PoC.svg?style=flat)
-[![Latest release](https://img.shields.io/github/release/VLSI-EDA/PoC.svg?style=flat)](https://github.com/VLSI-EDA/PoC/releases)
+![Latest tag](https://img.shields.io/github/tag/VHDL/PoC.svg?style=flat)
+[![Latest release](https://img.shields.io/github/release/VHDL/PoC.svg?style=flat)](https://github.com/VHDL/PoC/releases)
 
 <!--
 This library is published and maintained by **Chair for VLSI Design, Diagnostics and Architecture** - 
@@ -106,7 +106,7 @@ Protocol | Git Clone Command
 HTTPS    | `git clone --recursive https://github.com/VHDL/PoC.git PoC`
 SSH      | `git clone --recursive ssh://[email protected]:VHDL/PoC.git PoC`
 
-[221]: https://github.com/VLSI-EDA/PoC/archive/Vivado.zip
+[221]: https://github.com/VHDL/PoC/archive/master.zip
 [222]: http://VHDL.github.io/PoC/UsingPoC/Download.html
 
 ### 2.3 Configuring PoC on a Local System

diff --git a/docs/ChangeLog/2014/index.rst b/docs/ChangeLog/2014/index.rst
@@ -1,4 +1,4 @@
-.. _CHANGE:2014:
+.. _CHANGE/2014:
 
 2014
 ####

diff --git a/docs/ChangeLog/2015/index.rst b/docs/ChangeLog/2015/index.rst
@@ -1,4 +1,4 @@
-.. _CHANGE:2015:
+.. _CHANGE/2015:
 
 2015
 ####

diff --git a/docs/ChangeLog/2016/index.rst b/docs/ChangeLog/2016/index.rst
@@ -1,4 +1,4 @@
-.. _CHANGE:2016:
+.. _CHANGE/2016:
 
 2016
 ####

diff --git a/docs/ChangeLog/2016/v1.x.rst b/docs/ChangeLog/2016/v1.x.rst
@@ -10,36 +10,36 @@ Already documented changes are available on the ``release`` branch at GitHub.
 
 * New Entities
 
-  * :ref:`IP:ocram_sdp_wf`
-  * :ref:`IP:ocram_tdp_wf`
-  * :ref:`IP:cache_par2`
-  * :ref:`IP:cache_cpu`
-  * :ref:`IP:cache_mem`
-  * Simulation helper :ref:`IP:ocram_tdp_sim`
+  * :ref:`IP/ocram_sdp_wf`
+  * :ref:`IP/ocram_tdp_wf`
+  * :ref:`IP/cache_par2`
+  * :ref:`IP/cache_cpu`
+  * :ref:`IP/cache_mem`
+  * Simulation helper :ref:`IP/ocram_tdp_sim`
 
 * Updated Entities
 
-  * Interface of :ref:`IP:cache_tagunit_par` changed slightly.
-  * New port "write-mask" in :ref:`IP:ddr3_mem2mig_adapter_Series7`.
-  * New port "write-mask" in :ref:`IP:ddr2_mem2mig_adapter_Spartan6`.
-  * Fixed :ref:`IP:dstruct_deque`
+  * Interface of :ref:`IP/cache_tagunit_par` changed slightly.
+  * New port "write-mask" in :ref:`IP/ddr3_mem2mig_adapter_Series7`.
+  * New port "write-mask" in :ref:`IP/ddr2_mem2mig_adapter_Spartan6`.
+  * Fixed :ref:`IP/dstruct_deque`
 
 * New Testbenches
 
-  * Testbench for :ref:`IP:ocram_sdp_wf`
-  * Testbench for :ref:`IP:ocram_tdp_wf`
-  * Testbench for :ref:`IP:cache_par2`
-  * Testbench for :ref:`IP:cache_cpu`
-  * Testbench for :ref:`IP:cache_mem`
+  * Testbench for :ref:`IP/ocram_sdp_wf`
+  * Testbench for :ref:`IP/ocram_tdp_wf`
+  * Testbench for :ref:`IP/cache_par2`
+  * Testbench for :ref:`IP/cache_cpu`
+  * Testbench for :ref:`IP/cache_mem`
 
 * Updated Testbenches
 
-  * Testbench for :ref:`IP:ocram_sdp`
-  * Testbench for :ref:`IP:ocram_esdp`
-  * Testbench for :ref:`IP:ocram_tdp`
-  * Testbench for :ref:`IP:sortnet_BitonicSort`
-  * Testbench for :ref:`IP:sortnet_OddEvenSort`
-  * Testbench for :ref:`IP:sortnet_OddEvenMergeSort`
+  * Testbench for :ref:`IP/ocram_sdp`
+  * Testbench for :ref:`IP/ocram_esdp`
+  * Testbench for :ref:`IP/ocram_tdp`
+  * Testbench for :ref:`IP/sortnet_BitonicSort`
+  * Testbench for :ref:`IP/sortnet_OddEvenSort`
+  * Testbench for :ref:`IP/sortnet_OddEvenMergeSort`
 
 * New Constraints
 * Updated Constraints

diff --git a/docs/ConstraintFiles/Altera/CycloneIII/DE0.rst b/docs/ConstraintFiles/Altera/CycloneIII/DE0.rst
diff --git a/docs/ConstraintFiles/Altera/CycloneIII/DE0nano.rst b/docs/ConstraintFiles/Altera/CycloneIII/DE0nano.rst
diff --git a/docs/ConstraintFiles/Altera/CycloneIII/index.rst b/docs/ConstraintFiles/Altera/CycloneIII/index.rst
diff --git a/docs/ConstraintFiles/Altera/StratixIV/DE4.rst b/docs/ConstraintFiles/Altera/StratixIV/DE4.rst
diff --git a/docs/ConstraintFiles/Altera/StratixIV/index.rst b/docs/ConstraintFiles/Altera/StratixIV/index.rst
diff --git a/docs/ConstraintFiles/Altera/index.rst b/docs/ConstraintFiles/Altera/index.rst
@@ -2,17 +2,10 @@
 Altera
 ######
 
-  * Cyclone III
-    * DE0
-    * DE0 nano
-  * Stratix IV
-    * DE4
   * Stratix V
     * DE5
 
 .. toctree::
    :hidden:
 
-   CycloneIII/index
-   StratixIV/index
    StratixV/index
diff --git a/docs/ConstraintFiles/Xilinx/Spartan3/S3ESK.rst b/docs/ConstraintFiles/Xilinx/Spartan3/S3ESK.rst
diff --git a/docs/ConstraintFiles/Xilinx/Spartan3/S3SK.rst b/docs/ConstraintFiles/Xilinx/Spartan3/S3SK.rst
diff --git a/docs/ConstraintFiles/Xilinx/Spartan3/index.rst b/docs/ConstraintFiles/Xilinx/Spartan3/index.rst
diff --git a/docs/ConstraintFiles/Xilinx/Spartan6/Atlys.rst b/docs/ConstraintFiles/Xilinx/Spartan6/Atlys.rst
diff --git a/docs/ConstraintFiles/Xilinx/Spartan6/index.rst b/docs/ConstraintFiles/Xilinx/Spartan6/index.rst
diff --git a/docs/ConstraintFiles/Xilinx/Virtex5/ML505.rst b/docs/ConstraintFiles/Xilinx/Virtex5/ML505.rst
diff --git a/docs/ConstraintFiles/Xilinx/Virtex5/ML506.rst b/docs/ConstraintFiles/Xilinx/Virtex5/ML506.rst
diff --git a/docs/ConstraintFiles/Xilinx/Virtex5/XUPV5.rst b/docs/ConstraintFiles/Xilinx/Virtex5/XUPV5.rst
diff --git a/docs/ConstraintFiles/Xilinx/Virtex5/index.rst b/docs/ConstraintFiles/Xilinx/Virtex5/index.rst
diff --git a/docs/ConstraintFiles/Xilinx/Virtex6/ML605.rst b/docs/ConstraintFiles/Xilinx/Virtex6/ML605.rst
diff --git a/docs/ConstraintFiles/Xilinx/Virtex6/index.rst b/docs/ConstraintFiles/Xilinx/Virtex6/index.rst
diff --git a/docs/ConstraintFiles/Xilinx/index.rst b/docs/ConstraintFiles/Xilinx/index.rst
@@ -2,21 +2,10 @@
 Xilinx
 ######
 
- * Spartan-3 Boards
-    * Spartan-3 Starter Kit (S3SK)
-    * Spartan-3E Starter Kit (S3ESK)
- * Spartan-6 Boards
-    * Atlys
  * Artix-7
     * AC701
  * Kintex-7
     * KC705
- * Virtex-5
-    * ML505
-    * ML506
-    * XUPV5
- * Virtex-6
-    * ML605
  * Virtex-7
     * VC707
  * Zynq-7000
@@ -26,11 +15,7 @@ Xilinx
 .. toctree::
    :hidden:
 
-   Spartan3/index
-   Spartan6/index
    Artix7/index
    Kintex7/index
-   Virtex5/index
-   Virtex6/index
    Virtex7/index
    Zynq7000/index
diff --git a/docs/ConstraintFiles/index.rst b/docs/ConstraintFiles/index.rst
@@ -7,41 +7,32 @@ IP Core Constraint Files
 ************************
 
 * fifo
-* misc
-
-  * sync
-
 * net
 
   * eth
 
+* sync
 
 .. toctree::
    :hidden:
 
    fifo <fifo/index>
-   misc <misc/index>
    net <net/index>
+   sync <sync/index>
 
 
 Board Constraint Files
 **********************
 
 * Altera Boards
 
-  * Cyclone III
-  * Stratix IV
   * Stratix V
 
 * Lattice Boards
 * Xilinx Boards
 
   * Artix-7
   * Kintex-7
-  * Spartan-3 Boards
-  * Spartan-6 Boards
-  * Virtex-5
-  * Virtex-6
   * Virtex-7
   * Zynq-7000
 

diff --git a/docs/ConstraintFiles/misc/index.rst b/docs/ConstraintFiles/misc/index.rst
diff --git a/docs/ConstraintFiles/misc/sync/index.rst → docs/ConstraintFiles/sync/index.rst b/docs/ConstraintFiles/misc/sync/index.rst → docs/ConstraintFiles/sync/index.rst
diff --git a/docs/ConstraintFiles/misc/sync/sync_Bits.rst → docs/ConstraintFiles/sync/sync_Bits.rst b/docs/ConstraintFiles/misc/sync/sync_Bits.rst → docs/ConstraintFiles/sync/sync_Bits.rst
diff --git a/...onstraintFiles/misc/sync/sync_Command.rst → docs/ConstraintFiles/sync/sync_Command.rst b/...onstraintFiles/misc/sync/sync_Command.rst → docs/ConstraintFiles/sync/sync_Command.rst
diff --git a/.../ConstraintFiles/misc/sync/sync_Reset.rst → docs/ConstraintFiles/sync/sync_Reset.rst b/.../ConstraintFiles/misc/sync/sync_Reset.rst → docs/ConstraintFiles/sync/sync_Reset.rst
diff --git a/...ConstraintFiles/misc/sync/sync_Vector.rst → docs/ConstraintFiles/sync/sync_Vector.rst b/...ConstraintFiles/misc/sync/sync_Vector.rst → docs/ConstraintFiles/sync/sync_Vector.rst