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Use wildcard instead of explicitly listing v-files #3

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Use wildcard instead of explicitly listing v-files #3

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2 changes: 1 addition & 1 deletion src/Makefile
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Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,7 @@
SIM ?= icarus
TOPLEVEL_LANG ?= verilog

VERILOG_SOURCES += $(PWD)/tb.v $(PWD)/counter.v $(PWD)/decoder.v
VERILOG_SOURCES += $(wildcard $(PWD)/*.v)

# TOPLEVEL is the name of the toplevel module in your Verilog or VHDL file
TOPLEVEL = tb
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