Update project tt_um_asgerwenneb (AsgerWenneb/trt10-verilog)

[TinyTapeoutBot]

Update project tt_um_asgerwenneb to commit AsgerWenneb/trt10-verilog@3d59989

Project title: Custom SRAM
Tiles: 1x2
Workflow: https://github.com/AsgerWenneb/trt10-verilog/actions/runs/13819826816

[urish]

@AsgerWenneb we are not able to merge this project, since it has the following line in the verilog file:

  inout  wire [7:0] ua,       // Analog pins, only ua[5:0] can be used

The project does not use any analog pins, so the ua pin shouldn't be present in the verilog file.

In any case, we won't be able to manufacture this on the upcoming IHP shuttle, please see the Efabless Shutdown FAQ for details.

[AsgerWenneb]

Makes sense, thank you.

The design is just the analog 1x2 template with nothing in it, as I didn't get around to finishing anything after the efabless shudown.

@urish : Should I submit the fixed (still empty) version, or does it not matter?

[urish]

No, don't worry about it :)