RISC-V 5-Stage Pipelined CPU

This project is a fully functional RISC-V RV32I CPU implemented in Verilog with support for both privileged and unprivileged modes. It features a classic 5-stage pipeline (IF, ID, EX, MEM, WB), a virtual memory system using Sv32, and basic I/O via UART. It boots a 32-bit version of xv6, a Unix-like teaching OS, and passes official RISC-V compliance tests. The design was developed and simulated using Vivado.

Features

• RV32I base instruction set
• Zicsr extension for CSR instructions
• 5-Stage pipeline design
• Hazard detection, data forwarding, and pipeline control
• GShare Branch Predictor
• Privilege levels: Machine (M), Supervisor (S), and User (U)
• Trap delegation, trap vectors, and priviledge mode switching
• Unified Memory
• SV32 Virtual Memory System with page fault trapping
• UART with FIFO buffer for I/O

Testing

• Verified with official RISC-V rv32mi and rv32ui tests
• Boots 32-bit xv6 successfully

5-Stage

• Priviledged Diagram with control signals excluded
• Original Unpriviledged Diagram (without csr)

Resources Used

• Vivado
• KiCad for diagram
• Berkley's CS61C Reference Card
• riscv-tests
• 32 bit port of xv6