Popular repositories Loading

1. Multiplexer-Simulation-in-Vivado Multiplexer-Simulation-in-Vivado Public

   In this experiment, a 4:1 Multiplexer (MUX) is designed and simulated using Verilog HDL in various modeling styles: Gate-Level, Data Flow, Behavioral, and Structural.

   Verilog 1 235

2. Sequence-Detector Sequence-Detector Public

   1 137

3. VLSI-LAB-EXP-1 VLSI-LAB-EXP-1 Public

   Forked from navaneethans/VLSI-LAB-EXP-1

   Verilog

4. VLSI-LAB-EXP-2 VLSI-LAB-EXP-2 Public

   Forked from navaneethans/VLSI-LAB-EXP-2

   Verilog

5. VLSI-LAB-EXP-3 VLSI-LAB-EXP-3 Public

   Forked from navaneethans/VLSI-LAB-EXP-3

   Verilog

6. VLSI-LAB-EXP-4 VLSI-LAB-EXP-4 Public

   Forked from navaneethans/VLSI-LAB-EXP-4

   Verilog