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9 changes: 7 additions & 2 deletions checks/rvfi_reg_check.sv
Original file line number Diff line number Diff line change
Expand Up @@ -16,11 +16,16 @@ module rvfi_reg_check (
input clock, reset, check,
`RVFI_INPUTS
);
`rvformal_const_rand_reg [63:0] insn_order;
`rvformal_const_rand_reg [4:0] register_index;
reg [63:0] insn_order;
reg [4:0] register_index;
reg [`RISCV_FORMAL_XLEN-1:0] register_shadow = 0;
reg register_written = 0;

always @(posedge clock) begin
insn_order <= insn_order;
register_index <= register_index;
end

integer channel_idx;
always @(posedge clock) begin
if (reset) begin
Expand Down