V3.0 JLC order

Change log:

• Update manufacture part number and add the JLC parts number
• Tune resetdog circuit
• Tune latch-up protection circuits: increase recovery time, tune slew-rate control and allow for startup currents
• Fix power domain crossing issue between RF and STM units, and between COBC and EPS.
• Do not populate R69, R70 and R71, since on the flight model CSBI-JTAG interface won't be used
• Add some redundancy when the latch-up protection of the RF part is disabled: out of two STM pins, at least one should be high
• Add some redundancy to trigger the resetdog (RDT): two STM pins should come high for the trigger event to happen
• Fix the issue with WDT intervening the programming cycle: use pins 7 and 8 of JTAG connector to pull ~EN pin of WDT to the high level

STM Pinout changes:

• SPI pins for the communication with RF chip should be configured as open drain outputs
• CS for EPS should be inverted
• Pins to control the RDT: PB8 (RDT_Clear_1) and PB7 (RDT_Clear_2) should both be high to trigger the RDT
• Pins to control the latch-up protection of the RF part: at least one of either PA0 (RF_LATCHUP_DIS_1) or PA1 (RF_LATCHUP_DIS_2) should be high to disable the latch-up protection

COBC_v3.0.Gerber.tar.gz
STS1_COBC-top.csv
STS1_COBC_v3.0_JLCBOM.csv

V2.7

Change log:

• Add separate latch-up circuits for RF and STM parts
• Rework resetdog circuit
• Reposition DC-DC circuit
• Add new lines to the UCI bus: SWDIO, SWDCLK, SWO, NOT_RST and change UCI_COBC_3V3 to UCI_COBC_5V
• Add MCU supervisory circuit (3V cutoff)
• Add a temperature sensor near RF amplifier chip
• Add 3D models
• Increase minimum hole size from 0.2 to 0.3 mm

STM Pinout changes:

• Flash_CS moved from PB9 to PA4
• Dosi_En added on PB10
• WDT_Clear moved from PA9 to PB9
• RF_TMP added on PC0
• RF_LATCHUP_DIS added on PA0

V2.6

Added resetdog, new RF part and changed DC-DC design.

V2.5

• Add more LEDs for debugging
• Change SPI distribution and omit SPI4 as discussed in meetings
• Change some minor layout problems