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Change memory mapping
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@Siudya
Siudya committed Mar 21, 2024
1 parent d156583 commit d2fe2bf
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Showing 6 changed files with 41 additions and 92 deletions.
26 changes: 21 additions & 5 deletions src/main/scala/system/SoC.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -94,6 +94,23 @@ abstract class BaseSoC()(implicit p: Parameters) extends LazyModule with HasSoCP
val peripheralXbar = TLXbar()
val l3_xbar = TLXbar()
val l3_banked_xbar = TLXbar()

val memRange = Seq(
AddressSet(0x0080000000L, 0x07FFFFFFFL),
AddressSet(0x0100000000L, 0x0FFFFFFFFL),
AddressSet(0x0200000000L, 0x1FFFFFFFFL),
AddressSet(0x0400000000L, 0x3FFFFFFFFL),
AddressSet(0x0800000000L, 0x7FFFFFFFFL),
AddressSet(0x1000000000L, 0x07FFFFFFFL)
)
val periRange = Seq(
AddressSet(0x0000000000L, 0x07FFFFFFFL),
AddressSet(0x1080000000L, 0x07FFFFFFFL),
AddressSet(0x1100000000L, 0x0FFFFFFFFL),
AddressSet(0x1200000000L, 0x1FFFFFFFFL),
AddressSet(0x1400000000L, 0x3FFFFFFFFL),
AddressSet(0x1800000000L, 0x7FFFFFFFFL),
)
}

// We adapt the following three traits from rocket-chip.
Expand Down Expand Up @@ -135,9 +152,6 @@ trait HaveSlaveAXI4Port {
trait HaveAXI4MemPort {
this: BaseSoC =>
val device = new MemoryDevice

val memAddrMask = (1L << PAddrBits) - 1L
val memRange = AddressSet(0x00000000L, memAddrMask).subtract(AddressSet(0x00000000L, 0x7FFFFFFFL))
val memAXI4SlaveNode = AXI4SlaveNode(Seq(
AXI4SlavePortParameters(
slaves = Seq(
Expand Down Expand Up @@ -183,7 +197,7 @@ trait HaveAXI4MemPort {
trait HaveAXI4PeripheralPort { this: BaseSoC =>
// on-chip devices: 0x3800_0000 - 0x3fff_ffff 0x0000_0000 - 0x0000_0fff
val onChipPeripheralRange = AddressSet(0x38000000L, 0x07ffffffL)
val uartRange = AddressSet(0x40600000, 0xf)
val uartRange = AddressSet(0x40600000L, 0xFFFF)
val uartDevice = new SimpleDevice("serial", Seq("xilinx,uartlite"))
val uartParams = AXI4SlaveParameters(
address = Seq(uartRange),
Expand All @@ -193,7 +207,9 @@ trait HaveAXI4PeripheralPort { this: BaseSoC =>
resources = uartDevice.reg
)

val peripheralRange = AddressSet(0x00000000L, 0x7FFFFFFFL).subtract(onChipPeripheralRange).flatMap(x => x.subtract(uartRange))
val peripheralRange = periRange
.flatMap(_.subtract(onChipPeripheralRange))
.flatMap(_.subtract(uartRange))
val peripheralNode = AXI4SlaveNode(Seq(AXI4SlavePortParameters(
Seq(AXI4SlaveParameters(
address = peripheralRange,
Expand Down
2 changes: 1 addition & 1 deletion src/main/scala/top/Configs.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -347,6 +347,6 @@ class DefaultConfig(n: Int = 1) extends Config(
new WithNKBL3(4 * 1024, inclusive = false, banks = 4, ways = 8, core_num = n)
++ new WithNKBL2(256, inclusive = false, banks = 2, ways = 8, alwaysReleaseData = true)
++ new WithNKBL1D(64)
++ new BaseConfig(n)
++ new BaseConfig(n, true)
)

91 changes: 12 additions & 79 deletions src/main/scala/xiangshan/backend/execute/fu/PMA.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -94,69 +94,6 @@ trait MMPMAMethod extends PMAConst with PMAMethod with PMPReadWriteMethodBare {
}

trait PMAMethod extends PMAConst {
/**
* from CPU
* BASE TOP Size Description Attribute
* 0x00_0000_0000 0x00_0FFF_FFFF Reserved
* 0x00_1000_0000 0x00_1FFF_FFFF 256MB QSPI Flash RX
* 0x00_2000_0000 0x00_2FFF_FFFF Reserved
* 0x00_3000_0000 0x00_3000_FFFF 64KB GPU(V550) RW
* 0x00_3001_0000 0x00_3001_FFFF 64KB G71 RW
* 0x00_3002_0000 0x00_3003_FFFF Reserved
* 0x00_3004_0000 0x00_3004_FFFF 64KB DMA RW
* 0x00_3005_0000 0x00_3005_FFFF 64KB SDMMC RW
* 0x00_3006_0000 0x00_3015_FFFF 1MB USB RW
* 0x00_3016_0000 0x00_3025_FFFF 1MB DATA_CPU_BRIDGE RW
* 0x00_3026_0000 0x00_30FF_FFFF Reserved
* 0x00_3100_0000 0x00_3100_FFFF 64KB QSPI RW
* 0x00_3101_0000 0x00_3101_FFFF 64KB GMAC RW
* 0x00_3102_0000 0x00_3102_FFFF 64KB HDMI RW
* 0x00_3103_0000 0x00_3103_FFFF 64KB HDMI_PHY RW
* 0x00_3104_0000 0x00_3105_FFFF 128KB DP RW
* 0x00_3106_0000 0x00_3106_FFFF 64KB DDR0 RW
* 0x00_3107_0000 0x00_3107_FFFF 64KB DDR0_PHY RW
* 0x00_3108_0000 0x00_3108_FFFF 64KB DDR1 RW
* 0x00_3109_0000 0x00_3109_FFFF 64KB DDR1_PHY RW
* 0x00_310A_0000 0x00_310A_FFFF 64KB IIS RW
* 0x00_310B_0000 0x00_310B_FFFF 64KB UART0 RW
* 0x00_310C_0000 0x00_310C_FFFF 64KB UART1 RW
* 0x00_310D_0000 0x00_310D_FFFF 64KB UART2 RW
* 0x00_310E_0000 0x00_310E_FFFF 64KB IIC0 RW
* 0x00_310F_0000 0x00_310F_FFFF 64KB IIC1 RW
* 0x00_3110_0000 0x00_3110_FFFF 64KB IIC2 RW
* 0x00_3111_0000 0x00_3111_FFFF 64KB GPIO RW
* 0x00_3112_0000 0x00_3112_FFFF 64KB CRU RW
* 0x00_3113_0000 0x00_3113_FFFF 64KB WDT RW
* 0x00_3114_0000 0x00_3114_FFFF 64KB USB2_PHY0 RW
* 0x00_3115_0000 0x00_3115_FFFF 64KB USB2_PHY1 RW
* 0x00_3116_0000 0x00_3116_FFFF 64KB USB2_PHY2 RW
* 0x00_3117_0000 0x00_3117_FFFF 64KB USB2_PHY3 RW
* 0x00_3118_0000 0x00_3118_FFFF 64KB USB3_PHY0 RW
* 0x00_3119_0000 0x00_3119_FFFF 64KB USB3_PHY1 RW
* 0x00_311a_0000 0x00_311a_FFFF 64KB USB3_PHY2 RW
* 0x00_311b_0000 0x00_311b_FFFF 64KB USB3_PHY3 RW
* 0x00_311c_0000 0x00_311c_FFFF 64KB PCIE0_CFG RW
* 0x00_311d_0000 0x00_311d_FFFF 64KB PCIE1_CFG RW
* 0x00_311e_0000 0x00_311e_FFFF 64KB PCIE2_CFG RW
* 0x00_311f_0000 0x00_311f_FFFF 64KB PCIE3_CFG RW
* 0x00_3120_0000 0x00_3120_FFFF 64KB SYSCFG RW
* 0x00_3121_0000 0x00_3130_FFFF 1MB DATA_CPU_BRIDGE RW
* 0x00_3131_0000 0x00_37FF_FFFF Reserved
* 0x00_3800_0000 0x00_3800_FFFF 64KB CLINT (In cpu) RW
* 0x00_3801_0000 0x00_3801_FFFF Reserved
* 0x00_3802_0000 0x00_3802_0FFF 4KB Debug (In cpu) RW
* 0x00_3802_1000 0x00_38FF_FFFF Reserved
* 0x00_3900_0000 0x00_3900_0FFF 4KB CacheCtrl RW
* 0x00_3900_1000 0x00_3900_1FFF 4KB Core Reset RW
* 0x00_3900_2000 0x00_3BFF_FFFF Reserved
* 0x00_3C00_0000 0x00_3FFF_FFFF PLIC (In cpu) RW
* 0x00_4000_0000 0x00_4FFF_FFFF 256MB PCIe0 RW
* 0x00_5000_0000 0x00_5FFF_FFFF 256MB PCIe1 RW
* 0x00_6000_0000 0x00_6FFF_FFFF 256MB PCIe2 RW
* 0x00_7000_0000 0x00_7FFF_FFFF 256MB PCIe3 RW
* 0x00_8000_0000 0x1F_FFFF_FFFF 126GB DDR RWXIDSA
*/

def pma_init() : (Vec[UInt], Vec[UInt], Vec[UInt]) = {
def genAddr(init_addr: BigInt) = {
init_addr.U((PMPAddrBits - PMPOffBits).W)
Expand Down Expand Up @@ -188,22 +125,18 @@ trait PMAMethod extends PMAConst {
addr_list.append(genAddr(addr))
mask_list.append(genMask(addr, a))
}

addPMA(0x480000000L, c = true, atomic = true, a = 1, x = true, w = true, r = true)
addPMA(0x80000000L, a = 1, w = true, r = true)
addPMA(0x3b300000L, a = 1, x = true, r = true)
addPMA(0x3b1f0000L, a = 1, w = true, r = true)
addPMA(0x3b000000L, a = 1)
addPMA(0x39002000L, a = 1, w = true, r = true)
addPMA(0x39000000L, a = 1)
addPMA(0x38021000L, a = 1, w = true, r = true, x = true)
addPMA(0x38020000L, a = 1)
addPMA(0x38010000L, a = 1, w = true, r = true)
addPMA(0x38000000L, a = 1)
addPMA(0x31310000L, a = 1, w = true, r = true)
addPMA(0x30000000L, a = 1)
addPMA(0x20000000L, a = 1, w = true, x = true, r = true)
addPMA(0x10000000L, a = 1)
addPMA(0x0L, 0x2000000000L, a = 3, w = true, r = true)
addPMA(0x1080000000L, a = 1, c = true, atomic = true, x = true, w = true, r = true)
addPMA(0x107FE00000L, a = 1, c = true, atomic = true, x = true, w = true, r = true)
addPMA(0x0080000000L, a = 1, w = true, r = true)
addPMA(0x003B300000L, a = 1, r = true, x = true)
addPMA(0x003B1F0000L, a = 1, w = true, r = true)
addPMA(0x0038021000L, a = 1, w = true, r = true, x = true)
addPMA(0x0038020000L, a = 1, w = true, r = true)
addPMA(0x0037000000L, a = 1)
addPMA(0x0007200000L, a = 1, w = true, r = true, x = true)
addPMA(0x0002200000L, a = 1, w = true, r = true)
addPMA(0x000003FFFFL, a = 1, r = true, x = true)
addPMA(0)
while (cfg_list.length < NumPMA) {
addPMA(0)
Expand Down
2 changes: 1 addition & 1 deletion src/main/scala/xiangshan/mem/prefetch/SMSPrefetcher.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -1045,7 +1045,7 @@ class SMSPrefetcher(parentName: String = "Unknown")(implicit p: Parameters) exte
pf_filter.io.gen_req.valid := pht_gen_valid || agt_gen_valid || stride_gen_valid
pf_filter.io.gen_req.bits := pf_gen_req
io.tlb_req <> pf_filter.io.tlb_req
val is_valid_address = pf_filter.io.l2_pf_addr.bits > 0x80000000L.U
val is_valid_address = pf_filter.io.l2_pf_addr.bits >= 0x80000000L.U && pf_filter.io.l2_pf_addr.bits <= 0x1000000000L.U
io.pf_addr.valid := pf_filter.io.l2_pf_addr.valid && io.enable && is_valid_address
io.pf_addr.bits := pf_filter.io.l2_pf_addr.bits

Expand Down
10 changes: 5 additions & 5 deletions src/test/scala/top/SimMMIO.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -28,16 +28,16 @@ class SimMMIO(edge: AXI4EdgeParameters, dmaEdge: AXI4EdgeParameters)(implicit p:
val node = AXI4MasterNode(List(edge.master))
val dma_node = AXI4SlaveNode(List(dmaEdge.slave))

val flash = LazyModule(new AXI4Flash(Seq(AddressSet(0x10000000L, 0xfffffff))))
val uart = LazyModule(new AXI4UART(Seq(AddressSet(0x40600000L, 0xf))))
val flash = LazyModule(new AXI4Flash(Seq(AddressSet(0x00000000L, 0xFFFFFFF))))
val uart = LazyModule(new AXI4UART(Seq(AddressSet(0x40600000L, 0xFFFF))))
// val vga = LazyModule(new AXI4VGA(
// sim = false,
// fbAddress = Seq(AddressSet(0x50000000L, 0x3fffffL)),
// ctrlAddress = Seq(AddressSet(0x40001000L, 0x7L))
// ))
val sd = LazyModule(new AXI4DummySD(Seq(AddressSet(0x40002000L, 0xfff))))
val intrGen = LazyModule(new AXI4IntrGenerator(Seq(AddressSet(0x40070000L, 0x0000ffffL))))
val dmaGen = LazyModule(new AXI4FakeDMA(Seq(AddressSet(0x37030000L, 0x0000ffffL)), dmaEdge.master))
val sd = LazyModule(new AXI4DummySD(Seq(AddressSet(0x40002000L, 0xFFF))))
val intrGen = LazyModule(new AXI4IntrGenerator(Seq(AddressSet(0x40070000L, 0xFFFF))))
val dmaGen = LazyModule(new AXI4FakeDMA(Seq(AddressSet(0x37030000L, 0xFFFF)), dmaEdge.master))

val axiBus = AXI4Xbar()

Expand Down
2 changes: 1 addition & 1 deletion src/test/scala/top/SimTop.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -60,7 +60,7 @@ class SimTop(implicit p: Parameters) extends Module {
soc.scan_mode := false.B
soc.dft_lgc_rst_n := true.B.asAsyncReset
soc.dft_mode := false.B
soc.io.riscv_rst_vec.foreach(_ := 0x10000000L.U)
soc.io.riscv_rst_vec.foreach(_ := 0x00000000L.U)
soc.bootrom_disable := true.B
if(soc.dft.isDefined) {
soc.dft.get.cgen := false.B
Expand Down

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