arq: MFSK weak-signal backend + delivery-driven stop-and-wait rethink - #125

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rafael2k wants to merge 20 commits into

mercuryv2from

mfsk-arq-integration

Commits on Jul 31, 2026

modem: port v1's 32-MFSK (cl_mfsk) from C++ to C + MFSK-vs-FSK comparison

rafael2k
and
claude
committed
cb6cd96
docs: MFSK-PORT — add honest acquisition analysis

rafael2k
and
claude
committed
ebf9465
modem: port v1 OFDM framing subset for the MFSK mode (mfsk_ofdm.{c,h})

rafael2k
and
claude
committed
3a1fdbe
modem: port v1 MFSK preamble acquisition (time_sync_mfsk_corr) to C

rafael2k
and
claude
committed
dca49c2
docs: MFSK-PORT — end-to-end acquire+decode floor through ch (resolves the concern)

rafael2k
and
claude
committed
f2b3f4f
modem: wire rate-1/16 LDPC into the MFSK mode (encode/decode + coded floor)

rafael2k
and
claude
committed
17b6fec
modem: add MFSK postamble (dual-ended acquisition) + full mode comparison

rafael2k
and
claude
committed
3b3e4ec
modem: MFSK LDPC rate ladder (1/16..8/16) — rate is nearly free, 1/16 was wrong

rafael2k
and
claude
committed
9894c95
mfsk: port v1 detect_ack_pattern (control-plane pattern-ACK)

rafael2k
and
claude
committed
32a350e
modem: introduce modem_backend vtable; FreeDV as backend 1

rafael2k
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claude
committed
87f7cba
modem: MFSK weak-signal backend (backend 2)

rafael2k
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claude
committed
96931b0
arq: register MFSK as the OLLA bottom rung (below DATAC15)

rafael2k
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claude
committed
f18871e
arq: rethink data plane — delivery-driven stop-and-wait + pattern ACK

rafael2k
and
claude
committed
25b7cef
arq/modem: fix connect turnaround + MFSK data RX in the live path

rafael2k
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claude
committed
2de7a03
tests: build libfreedvdata.a on demand so `make test` works from a clean checkout

rafael2k
and
claude
committed
ce33622
tests: 2-arg notify fakes in test_arq_ladder

rafael2k
and
claude
committed
68f46fa
tests: wire test_freedv_harq into the suite after rebase onto trunk

rafael2k
and
claude
committed
231875b
modem/mfsk: postamble-anchored sync fallback for clipped-head bursts

rafael2k
and
claude
committed
7732b02
arq/fsm: IRS mirrors the ISS delivery-driven ladder

rafael2k
and
claude
committed
6796065
arq: port LISTEN OFF as a radio release into the rewritten FSM

rafael2k
and
claude
committed
c159feb

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arq: MFSK weak-signal backend + delivery-driven stop-and-wait rethink - #125

arq: MFSK weak-signal backend + delivery-driven stop-and-wait rethink#125
rafael2k wants to merge 20 commits into
mercuryv2from
mfsk-arq-integration

Commits on Jul 31, 2026

modem: port v1's 32-MFSK (cl_mfsk) from C++ to C + MFSK-vs-FSK comparison

docs: MFSK-PORT — add honest acquisition analysis

modem: port v1 OFDM framing subset for the MFSK mode (mfsk_ofdm.{c,h})

modem: port v1 MFSK preamble acquisition (time_sync_mfsk_corr) to C

docs: MFSK-PORT — end-to-end acquire+decode floor through ch (resolves the concern)

modem: wire rate-1/16 LDPC into the MFSK mode (encode/decode + coded floor)

modem: add MFSK postamble (dual-ended acquisition) + full mode comparison

modem: MFSK LDPC rate ladder (1/16..8/16) — rate is nearly free, 1/16 was wrong

mfsk: port v1 detect_ack_pattern (control-plane pattern-ACK)

modem: introduce modem_backend vtable; FreeDV as backend 1

modem: MFSK weak-signal backend (backend 2)

arq: register MFSK as the OLLA bottom rung (below DATAC15)

arq: rethink data plane — delivery-driven stop-and-wait + pattern ACK

arq/modem: fix connect turnaround + MFSK data RX in the live path

tests: build libfreedvdata.a on demand so `make test` works from a clean checkout

tests: 2-arg notify fakes in test_arq_ladder

tests: wire test_freedv_harq into the suite after rebase onto trunk

modem/mfsk: postamble-anchored sync fallback for clipped-head bursts

arq/fsm: IRS mirrors the ISS delivery-driven ladder

arq: port LISTEN OFF as a radio release into the rewritten FSM