Refine the reject for LDS

[chicyang]

Motivation

• Allow padded MX-scale layouts on gfx1250 (previously LdsBlockSizePerPadMXSA/MXSB > 0 was fully rejected)
• Reject the incoherent iterate-mode + LdsBlockSizePerPad=0 combo that otherwise crashed codegen with ZeroDivisionError.

Technical Details

• Solution.py: remove the gfx1250 blanket reject on LdsBlockSizePerPadMXSA/B > 0; add a reject for iterate-mode enabled while LdsBlockSizePerPad=0 (per
  A/B tensor).
• KernelWriterAssembly.py: move the tile_dim1==0 guard before the division in _emitTdmIterateInit so it raises a clear error instead of ZeroDivisionError.

Test Plan

Tox

Test Result

Submission Checklist

• Look over the contributing guidelines at https://github.com/ROCm/ROCm/blob/develop/CONTRIBUTING.md#pull-requests.

[codecov-commenter]

Codecov Report

❌ Patch coverage is 16.66667% with 5 lines in your changes missing coverage. Please review.

Files with missing lines	Patch %	Lines
...lt/tensilelite/Tensile/SolutionStructs/Solution.py	25.00%	3 Missing ⚠️
...blaslt/tensilelite/Tensile/KernelWriterAssembly.py	0.00%	2 Missing ⚠️

❌ Your project status has failed because the head coverage (77.89%) is below the target coverage (80.00%). You can increase the head coverage or adjust the target coverage.

Additional details and impacted files

@@             Coverage Diff             @@
##           develop    #8759      +/-   ##
===========================================
- Coverage    71.43%   71.43%   -0.00%     
===========================================
  Files         2612     2612              
  Lines       406993   407001       +8     
  Branches     60771    60774       +3     
===========================================
- Hits        290731   290727       -4     
- Misses       94958    94971      +13     
+ Partials     21304    21303       -1     

Flag	Coverage Δ		*Carryforward flag
TensileLite	76.81% <16.67%> (-0.01%)	⬇️
hipBLAS	90.81% <ø> (ø)		Carriedforward from 3b257bc
hipBLASLt	41.33% <ø> (-0.02%)	⬇️
hipCUB	82.68% <ø> (ø)		Carriedforward from 3b257bc
hipDNN	86.71% <ø> (ø)		Carriedforward from 3b257bc
hipFFT	50.79% <ø> (ø)		Carriedforward from 3b257bc
hipRAND	76.12% <ø> (ø)		Carriedforward from 3b257bc
hipSOLVER	69.18% <ø> (ø)		Carriedforward from 3b257bc
hipSPARSE	86.55% <ø> (ø)		Carriedforward from 3b257bc
rocBLAS	48.08% <ø> (ø)		Carriedforward from 3b257bc
rocFFT	47.22% <ø> (ø)		Carriedforward from 3b257bc
rocRAND	57.07% <ø> (ø)		Carriedforward from 3b257bc
rocSOLVER	77.89% <ø> (ø)		Carriedforward from 3b257bc
rocSPARSE	72.37% <ø> (ø)		Carriedforward from 3b257bc
rocThrust	91.34% <ø> (ø)		Carriedforward from 3b257bc

*This pull request uses carry forward flags. Click here to find out more.

Files with missing lines	Coverage Δ
...blaslt/tensilelite/Tensile/KernelWriterAssembly.py	69.51% <0.00%> (ø)
...lt/tensilelite/Tensile/SolutionStructs/Solution.py	58.88% <25.00%> (-0.01%)	⬇️

... and 3 files with indirect coverage changes

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