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cpu/esp32: fix periph/sdmmc for ESP32-S3 - #23010
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Since ESP-IDF v6.x, the clock configuration of an SDMMC slot is applied with the next transaction, which also resets the phase of the input clock. The phase of the input clock required on ESP32-S3 for MMCs was therefore overwritten. It is now configured with sdmmc_host_set_input_delay instead of writing it directly into the CLOCK register. SDMMC_DELAY_PHASE_3 corresponds to the value 6 used before. Assisted-by: Claude Code Opus 5.5
On ESP32-S3, the phase of the SDMMC input clock was always set to 270 degrees, which is required for MMCs. With SD Memory Cards, this phase leads to response errors for nearly each command, which were ignored as a workaround, and to sporadic failures of the card initialization or the first accesses, e.g. when mounting a file system. SD Memory Cards are now used with the default phase of 0 degrees as in ESP-IDF, and 270 degrees is only used for MMCs. Both phases can be overridden with CONFIG_SDMMC_INPUT_DELAY_PHASE_SD and CONFIG_SDMMC_INPUT_DELAY_PHASE_MMC. Assisted-by: Claude Code Opus 5.5
ESP-IDF v6.x checks in sd_host_check_buffer_alignment whether the buffer of a data transfer can be used for DMA, including its length given by sdmmc_command_t::buflen. Since buflen was not set, the check failed with "buffer can not be used for DMA" for each data transfer, e.g. for reading the SCR with ACMD51 during card initialization. Assisted-by: Claude Code Opus 5.5
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Contribution description
This PR fixes a small issue in
periph/sdmmcfor ESP32-S3 SoCs.The PR includes the following fixes:
On ESP32-S3, the phase of the SDMMC input clock was always set to 270 degrees, which is required for MMCs. With SD Memory Cards, this phase leads to response errors for nearly each command, which were ignored as a workaround, and to sporadic failures of the card initialization or the first accesses, e.g. when mounting a file system. SD Memory Cards are now used with the default phase of 0 degrees as in ESP-IDF, and 270 degrees is only used for MMCs. Both phases can be overridden with
CONFIG_SDMMC_INPUT_DELAY_PHASE_SDandCONFIG_SDMMC_INPUT_DELAY_PHASE_MMC.Since ESP-IDF v6.x (also applies for ESP-IDF 5.4), the clock configuration of an SDMMC slot is applied with the next transaction, which also resets the phase of the input clock. The phase of the input clock required on ESP32-S3 for MMCs was therefore overwritten. It is now configured with
sdmmc_host_set_input_delayinstead of writing it directly into the CLOCK register.The issue was identified during the migration to ESP-IDF v6.1 in PR #22946. This PR is a split-off from of PR #22946 and simplifies PR #22946.
Testing procedure
Compile an flash the
tests/sys/vfs_defaultto any ESP32-S3 board with SDMMC interface, e.g.:Issues/PRs references
Split-off from PR #22946
Declaration of AI-Tools / LLMs usage:
AI-Tools / LLMs that were used are: