[H2BLB] Describe the scheduling event for our generic processor

This commit describes the previously defined scheduling events on our generic
processor.

The insteresting things are:
1. The use of the InstRW to attach some scheduling events on an instruction.
2. The use of read advance to consume latency within a read.

`#1` is particularly insteresting because it may seem redundant with our
already defined global `LoadLatency` in the scheduling model.
It is in fact not redundant because if an instruction doesn't have its
how SchedWrite event, it can feed into a ReadAdvance construct and thus
we would get the benefits of the read advance.

llvm/lib/Target/H2BLB/H2BLBSchedModel.td

@@ -16,3 +16,28 @@ def H2BLBDefaultModel : SchedMachineModel {
 
   let CompleteModel = 0;
 }
+
+let SchedModel = H2BLBDefaultModel in {
+
+let BufferSize = 1 in {
+def ALURes : ProcResource<1>;
+def MemRes : ProcResource<1>;
+} // end BufferSize = 1.
+
+let Latency = 3 in
+def DefaultWriteLoad : SchedWriteRes<[MemRes]>;
+
+let Latency = 2 in
+def : WriteRes<WriteWSMUL, [ALURes]>;
+def : ReadAdvance<ReadWSMULArg0, 0>;
+def : ReadAdvance<ReadWSMULArg1, 1>;
+
+def : WriteRes<WriteWUMUL, [ALURes]>;
+def : ReadAdvance<ReadWUMULArg0, 0>;
+def : ReadAdvance<ReadWUMULArg1, 0>;
+
+// Setup the scheduling class for all loads, excluding
+// load of immediate value.
+def : InstRW<[DefaultWriteLoad], (instregex "^LD[^i]*$")>;
+
+} // end SchedMachineModel = H2BLBDefaultModel.

llvm/test/CodeGen/H2BLB/sched.mir

@@ -1,6 +1,10 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
 # RUN: llc -mtriple h2blb -run-pass machine-scheduler  -o - %s | FileCheck %s -check-prefixes=DEFAULT
 # RUN: llc -mtriple h2blb -run-pass machine-scheduler  -o - %s -mcpu generic | FileCheck %s -check-prefixes=GENERIC
+
+# The read advance of the WSMUL comsumes one cycle of the latency of the LDR16.
+# Therefore only one instruction needs to be scheduling between these
+# two instructions.
 ---
 name: sched
 tracksRegLiveness: true
@@ -31,8 +35,8 @@ body:             |
     ; GENERIC-NEXT: [[COPY2:%[0-9]+]]:gpr16 = COPY $r3
     ; GENERIC-NEXT: [[LDR16_:%[0-9]+]]:gpr16 = LDR16 [[COPY2]], 0
     ; GENERIC-NEXT: [[ADDi16rr:%[0-9]+]]:gpr16 = ADDi16rr [[COPY]], [[COPY1]]
-    ; GENERIC-NEXT: [[ADDi16rr1:%[0-9]+]]:gpr16 = ADDi16rr [[ADDi16rr]], [[ADDi16rr]]
     ; GENERIC-NEXT: [[WIDENING_SMUL:%[0-9]+]]:gpr32 = WIDENING_SMUL [[COPY]], [[LDR16_]]
+    ; GENERIC-NEXT: [[ADDi16rr1:%[0-9]+]]:gpr16 = ADDi16rr [[ADDi16rr]], [[ADDi16rr]]
     ; GENERIC-NEXT: [[ADDi16rr2:%[0-9]+]]:gpr16 = ADDi16rr [[ADDi16rr1]], [[ADDi16rr1]]
     ; GENERIC-NEXT: [[ADDi16rr3:%[0-9]+]]:gpr16 = ADDi16rr [[ADDi16rr2]], [[WIDENING_SMUL]].sub_low16
     ; GENERIC-NEXT: $r1 = COPY [[ADDi16rr3]]
@@ -49,3 +53,53 @@ body:             |
     $r1 = COPY %8
     RETURN implicit $r0, implicit $r1
 ...
+# WUMUL doesn't have read advance so the full two stall must be observed.
+# (Or they must be filled with two instructions.)
+---
+name: sched_umul
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $r0, $r1, $r2, $r3
+
+    ; DEFAULT-LABEL: name: sched_umul
+    ; DEFAULT: liveins: $r0, $r1, $r2, $r3
+    ; DEFAULT-NEXT: {{  $}}
+    ; DEFAULT-NEXT: [[COPY:%[0-9]+]]:gpr16 = COPY $r1
+    ; DEFAULT-NEXT: [[COPY1:%[0-9]+]]:gpr16 = COPY $r2
+    ; DEFAULT-NEXT: [[COPY2:%[0-9]+]]:gpr16 = COPY $r3
+    ; DEFAULT-NEXT: [[LDR16_:%[0-9]+]]:gpr16 = LDR16 [[COPY2]], 0
+    ; DEFAULT-NEXT: [[ADDi16rr:%[0-9]+]]:gpr16 = ADDi16rr [[COPY]], [[COPY1]]
+    ; DEFAULT-NEXT: [[ADDi16rr1:%[0-9]+]]:gpr16 = ADDi16rr [[ADDi16rr]], [[ADDi16rr]]
+    ; DEFAULT-NEXT: [[ADDi16rr2:%[0-9]+]]:gpr16 = ADDi16rr [[ADDi16rr1]], [[ADDi16rr1]]
+    ; DEFAULT-NEXT: [[WIDENING_UMUL:%[0-9]+]]:gpr32 = WIDENING_UMUL [[COPY]], [[LDR16_]]
+    ; DEFAULT-NEXT: [[ADDi16rr3:%[0-9]+]]:gpr16 = ADDi16rr [[ADDi16rr2]], [[WIDENING_UMUL]].sub_low16
+    ; DEFAULT-NEXT: $r1 = COPY [[ADDi16rr3]]
+    ; DEFAULT-NEXT: RETURN implicit $r0, implicit $r1
+    ;
+    ; GENERIC-LABEL: name: sched_umul
+    ; GENERIC: liveins: $r0, $r1, $r2, $r3
+    ; GENERIC-NEXT: {{  $}}
+    ; GENERIC-NEXT: [[COPY:%[0-9]+]]:gpr16 = COPY $r1
+    ; GENERIC-NEXT: [[COPY1:%[0-9]+]]:gpr16 = COPY $r2
+    ; GENERIC-NEXT: [[COPY2:%[0-9]+]]:gpr16 = COPY $r3
+    ; GENERIC-NEXT: [[LDR16_:%[0-9]+]]:gpr16 = LDR16 [[COPY2]], 0
+    ; GENERIC-NEXT: [[ADDi16rr:%[0-9]+]]:gpr16 = ADDi16rr [[COPY]], [[COPY1]]
+    ; GENERIC-NEXT: [[ADDi16rr1:%[0-9]+]]:gpr16 = ADDi16rr [[ADDi16rr]], [[ADDi16rr]]
+    ; GENERIC-NEXT: [[WIDENING_UMUL:%[0-9]+]]:gpr32 = WIDENING_UMUL [[COPY]], [[LDR16_]]
+    ; GENERIC-NEXT: [[ADDi16rr2:%[0-9]+]]:gpr16 = ADDi16rr [[ADDi16rr1]], [[ADDi16rr1]]
+    ; GENERIC-NEXT: [[ADDi16rr3:%[0-9]+]]:gpr16 = ADDi16rr [[ADDi16rr2]], [[WIDENING_UMUL]].sub_low16
+    ; GENERIC-NEXT: $r1 = COPY [[ADDi16rr3]]
+    ; GENERIC-NEXT: RETURN implicit $r0, implicit $r1
+    %0:gpr16 = COPY $r1
+    %1:gpr16 = COPY $r2
+    %2:gpr16 = COPY $r3
+    %3:gpr16 = LDR16 %2, 0
+    %4:gpr32 = WIDENING_UMUL %0, %3
+    %5:gpr16 = ADDi16rr %0, %1
+    %6:gpr16 = ADDi16rr %5, %5
+    %7:gpr16 = ADDi16rr %6, %6
+    %8:gpr16 = ADDi16rr %7, %4.sub_low16
+    $r1 = COPY %8
+    RETURN implicit $r0, implicit $r1
+...