Rework UART, add basic SPI driver

CMakeLists.txt

@@ -32,7 +32,7 @@ enable_language(ASM)
 
 set(CMAKE_EXECUTABLE_SUFFIX ".elf")
 set(CMAKE_C_FLAGS "${MCPU} -std=gnu11 ${MFPU} ${MFLOAT_ABI} ${RUNTIME_LIBRARY} -mthumb -Wall -Werror")
-set(CMAKE_CXX_FLAGS "${MCPU} -std=c++17 ${MFPU} ${MFLOAT_ABI} ${RUNTIME_LIBRARY} -mthumb -Wall -Werror")
+set(CMAKE_CXX_FLAGS "${MCPU} -std=c++20 ${MFPU} ${MFLOAT_ABI} ${RUNTIME_LIBRARY} -mthumb -Wall -Werror")
 set(CMAKE_EXE_LINKER_FLAGS "-T${LINKER_SCRIPT} ${RUNTIME_LIBRARY_SYSCALLS} -Wl,-Map=test.map -Wl,--gc-sections -static -Wl,--start-group -lc -lm -Wl,--end-group -u _printf_float")
 set(CMAKE_ASM_FLAGS "${CMAKE_C_FLAGS} -x assembler-with-cpp")
 
@@ -44,7 +44,7 @@ add_subdirectory(thirdparty)
 add_executable(
   ${PROJECT_NAME}
   src/main.cpp
-  src/interrupts.c
+  src/interrupts.cpp
   bsp/system/syscalls.c
   bsp/system/sysmem.c
   bsp/system/system_stm32h5xx.c
@@ -74,6 +74,7 @@ target_include_directories(
   ${PROJECT_NAME}
   PRIVATE
   bsp
+  bsp/thirdparty/etl/include
 )
 
 add_custom_command(TARGET ${CMAKE_PROJECT_NAME} POST_BUILD COMMAND ${CMAKE_SIZE} $<TARGET_FILE:${CMAKE_PROJECT_NAME}>)

bsp/CMakeLists.txt

@@ -5,6 +5,7 @@ add_library(bsplib
 	drivers/i2c/i2c.cpp
 	drivers/sd/sd.cpp
 	drivers/uart/uart.cpp
+	drivers/spi/spi.cpp
 	proxy/logger/logger.cpp
 )
 
@@ -15,5 +16,7 @@ target_include_directories(
 	${CMAKE_SOURCE_DIR}/thirdparty/cmsis-device-h5/Include
 	${CMAKE_SOURCE_DIR}/thirdparty/STM32CubeH5/Drivers/STM32H5xx_HAL_Driver/Inc
 	${CMAKE_SOURCE_DIR}/thirdparty/fatfs/source
+	${CMAKE_SOURCE_DIR}/thirdparty/etl/include
 	${CMAKE_SOURCE_DIR}/bsp
+	${CMAKE_SOURCE_DIR}/src
 )

bsp/drivers/clock/clock.cpp

@@ -51,25 +51,27 @@ clock_setup_HSE(uint8_t M, uint32_t N, uint8_t Q, uint8_t P)
   uint8_t pll2_m = 16;
   uint32_t pll2_n = 192;
   uint8_t pll2_r = 4;
-  	  // set as 100 MHz
-    RCC->CR &= ~RCC_CR_PLL2ON;
-
-    // Set source for PLL 1
-    RCC->PLL2CFGR |= (pll2_m << RCC_PLL2CFGR_PLL2M_Pos); // Set dividers for PLL 1
-    //Enable outputs $
-    RCC->PLL2CFGR |= RCC_PLL2CFGR_PLL2REN;
-
-    RCC->PLL2DIVR |= ((pll2_r-1) << RCC_PLL2DIVR_PLL2R_Pos | ((pll2_n-1)&RCC_PLL2DIVR_PLL2N) );
-    // Set HSE as source for PLL 1
-    RCC->PLL2CFGR |= 3 << RCC_PLL2CFGR_PLL2SRC_Pos;
-    // Enable PLL 1
-    RCC->CR |= RCC_CR_PLL2ON;
-
-    // Wait for PLL to stabilize
-    while (!(RCC->CR & RCC_CR_PLL2RDY_Msk))
-      ;
-    // Makes SDMMC use PLL 2
-    RCC->CCIPR4 |= (1 << RCC_CCIPR4_SDMMC1SEL_Pos);
+  // set as 100 MHz
+  RCC->CR &= ~RCC_CR_PLL2ON;
+
+  // Set source for PLL 2
+  RCC->PLL2CFGR |= (pll2_m << RCC_PLL2CFGR_PLL2M_Pos); // Set dividers for PLL 1
+  //Enable outputs $
+  RCC->PLL2CFGR |= RCC_PLL2CFGR_PLL2REN;
+
+  RCC->PLL2DIVR |= ((pll2_r - 1) << RCC_PLL2DIVR_PLL2R_Pos | ((pll2_n - 1) & RCC_PLL2DIVR_PLL2N));
+  // Set HSE as source for PLL 1
+  RCC->PLL2CFGR |= 3 << RCC_PLL2CFGR_PLL2SRC_Pos;
+  // Enable PLL 2
+  RCC->CR |= RCC_CR_PLL2ON;
+
+  // Wait for PLL to stabilize
+  while (!(RCC->CR & RCC_CR_PLL2RDY_Msk))
+    ;
+  // Makes SDMMC use PLL 2
+  RCC->CCIPR4 |= (1 << RCC_CCIPR4_SDMMC1SEL_Pos);
+
+  RCC->AHB1ENR |= RCC_AHB1ENR_BKPRAMEN;
 }
 static uint32_t ticks = 0;
 
@@ -81,11 +83,7 @@ sleep_ms(uint32_t ms)
     ;
 }
 
-
-
-extern "C"{
-
-
+extern "C" {
 
 void
 SysTick_Handler(void)
@@ -99,12 +97,15 @@ SysTick_get_tick_count()
   return ticks;
 }
 
-uint32_t HAL_GetTick(){
-	return ticks;
+uint32_t
+HAL_GetTick()
+{
+  return ticks;
 }
 
-void HAL_Delay(uint32_t t){
-	sleep_ms(t);
+void
+HAL_Delay(uint32_t t)
+{
+  sleep_ms(t);
 }
-
 }

bsp/drivers/sd/sd.cpp

@@ -35,7 +35,7 @@ sd_init()
   hsd1.Instance = SDMMC1;
   hsd1.Init.ClockEdge = SDMMC_CLOCK_EDGE_RISING;
   hsd1.Init.ClockPowerSave = SDMMC_CLOCK_POWER_SAVE_DISABLE;
-  hsd1.Init.BusWide = SDMMC_BUS_WIDE_4B; // Start with 1-bit
+  hsd1.Init.BusWide = SDMMC_BUS_WIDE_4B;
   hsd1.Init.HardwareFlowControl = SDMMC_HARDWARE_FLOW_CONTROL_DISABLE;
   hsd1.Init.ClockDiv = 3;
   if (HAL_SD_Init(&hsd1) == HAL_OK)

bsp/drivers/spi/spi.cpp

@@ -0,0 +1,87 @@
+#include "spi.hpp"
+
+#include "stm32h533xx.h"
+
+uint8_t*
+SPI3_xfer(uint8_t* data, uint8_t size)
+{
+  // Set SPI to transmit mode
+  SPI3->CR1 &= ~SPI_CR1_SPE;
+  SPI3->CR2 = size;
+  SPI3->CR1 |= SPI_CR1_SPE;
+  static uint8_t recv[128];
+
+  for (uint16_t i = 0; i < size; i++)
+  {
+    SPI3->TXDR = data[i];
+    recv[i] = SPI3->RXDR;
+    //	        while (!(SPI4->SR & SPI_SR_TXC)); // Wait for transfer completion
+  }
+  return recv;
+}
+
+void
+SPI4_Receive_HalfDuplex(uint8_t* data, uint16_t size)
+{
+  SPI4->CR1 &= ~SPI_CR1_SPE;
+  SPI4->CR1 &= ~SPI_CR1_HDDIR; // BIDIOE = 0 for receive
+  SPI4->CR2 = size;
+  SPI4->CR1 |= SPI_CR1_SPE;
+
+  for (uint16_t i = 0; i < size; i++)
+  {
+    SPI4->CR1 |= SPI_CR1_HDDIR;
+    SPI4->TXDR = 0xFF;
+    SPI4->CR1 &= ~SPI_CR1_HDDIR;
+    while (!(SPI4->SR & SPI_SR_RXP))
+      ;
+    data[i] = SPI4->RXDR;
+  }
+}
+
+void
+SPI4_Transmit_HalfDuplex(uint8_t* data, uint16_t size)
+{
+  SPI4->CR1 &= ~SPI_CR1_SPE;
+  SPI4->CR1 |= SPI_CR1_HDDIR; // Set transmitte
+  SPI4->CR2 = size;
+  SPI4->CR1 |= SPI_CR1_SPE;
+
+  for (uint16_t i = 0; i < size; i++)
+  {
+    SPI4->TXDR = data[i];
+  }
+}
+
+void
+SPI4_setup()
+{
+  RCC->APB2ENR |= RCC_APB2ENR_SPI4EN;
+
+  RCC->CCIPR3 &= ~RCC_CCIPR3_SPI4SEL;
+  SPI4->CR1 &= ~SPI_CR1_SPE; // Clear SPE bit using the defined bit mask
+  SPI4->CR1 = 0;             // Reset CR1 for clean configuration
+
+  SPI4->CFG1 = 0;
+  SPI4->CFG2 = 0;
+  SPI4->CFG1 &= ~(SPI_CFG1_MBR | SPI_CFG1_DSIZE);
+  SPI4->CFG1 |= (1 << SPI_CFG1_MBR_Pos) | (7 << SPI_CFG1_DSIZE_Pos);
+
+  SPI4->CFG2 |= (1 << SPI_CFG2_AFCNTR_Pos) | SPI_CFG2_MASTER | (0b11 << SPI_CFG2_COMM_Pos);
+
+  // 4. Enable SPI4
+  SPI4->IFCR |= SPI_IFCR_MODFC;
+  SPI4->CR1 |= SPI_CR1_SPE;
+}
+
+void
+SPI3_setup()
+{
+  RCC->APB1LENR |= RCC_APB1LENR_SPI3EN;
+  SPI3->CR1 &= ~SPI_CR1_SPE; // Clear SPE bit using the defined bit mask
+  SPI3->CR1 = 0;             // Reset CR1 for clean configuration
+  SPI3->CFG1 &= ~(SPI_CFG1_MBR | SPI_CFG1_DSIZE);
+  SPI3->CFG1 |= (0b100 << SPI_CFG1_MBR_Pos) | (7 << SPI_CFG1_DSIZE_Pos);
+  SPI3->CFG2 |= (1 << SPI_CFG2_MASTER_Pos);
+  SPI3->CR1 |= SPI_CR1_SPE;
+}

bsp/drivers/spi/spi.hpp

@@ -0,0 +1,17 @@
+#pragma once
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+#include <stdint.h>
+
+void SPI4_setup();
+void SPI4_Transmit_HalfDuplex(uint8_t *data, uint16_t size);
+void SPI4_Receive_HalfDuplex(uint8_t *data, uint16_t size);
+
+void SPI3_setup();
+uint8_t* SPI3_xfer(uint8_t* data, uint8_t size);
+
+#ifdef __cplusplus
+}
+#endif

bsp/drivers/uart/uart.cpp

@@ -1,14 +1,67 @@
 #include "uart.hpp"
-
 #include "config.h"
 
 #include <stdint.h>
 #include <string.h>
 
+#include "etl/queue.h"
+#include "etl/string.h"
+
 #include "stm32h533xx.h"
 
 uint8_t uart4_busy = 0;
-uint8_t gotMessage = false;
+
+Uart::Uart(uint8_t port_id, int interruptId) : callback(*this), port_id(port_id)
+{
+  GetInterruptVectorsInstance().register_callback(interruptId, callback);
+  if (port_id == 4)
+  {
+    uart4_setup();
+    receive_to_idle();
+  }
+}
+
+// Handler for interrupts from the UART.
+void
+Uart::InterruptHandler(const size_t id)
+{
+  if (UART4->ISR & USART_ISR_IDLE)
+  {
+    UART4->ICR |= USART_ICR_IDLECF;
+
+    if (GPDMA1_Channel1->CCR & DMA_CCR_EN)
+    {
+      *((uint8_t*) GPDMA1_Channel1->CDAR) = 0;
+      GPDMA1_Channel1->CCR |= DMA_CCR_SUSP;
+      while (!(GPDMA1_Channel1->CSR & DMA_CSR_SUSPF))
+        ;
+      GPDMA1_Channel1->CCR |= DMA_CCR_RESET;
+      // __uart4_received_message(uart4_receive_buffer);
+      if (_queue.size() < max_messages_no)
+        _queue.push((const char*) _raw_rx);
+      receive_to_idle();
+    }
+  }
+}
+bool
+Uart::data_received(etl::string<RX_BUFFER_SIZE>& str)
+{
+  if (_queue.empty())
+    return false;
+  //	str = std::move(queue.front());
+  _queue.pop_into(str);
+  return true;
+}
+
+void
+Uart::receive_to_idle()
+{
+  UART4->ICR |= USART_ICR_IDLECF;
+  GPDMA1_Channel1->CBR1 = RX_BUFFER_SIZE - 1;
+  GPDMA1_Channel1->CDAR = (uint32_t) _raw_rx;
+  GPDMA1_Channel1->CSAR = (uint32_t) &UART4->RDR;
+  GPDMA1_Channel1->CCR = DMA_CCR_EN;
+}
 
 void
 print(const char* str)
@@ -18,26 +71,23 @@ print(const char* str)
   while (uart4_busy)
     ;
   uart4_busy = 1;
-  uint32_t bytes_amount = strlen(str);
+  uint32_t bytes_amount = etl::strlen(str);
   GPDMA1_Channel0->CBR1 = bytes_amount;
   GPDMA1_Channel0->CSAR = (uint32_t) str;
   GPDMA1_Channel0->CDAR = (uint32_t) &UART4->TDR;
   UART4->ICR |= USART_ICR_TCCF;
   GPDMA1_Channel0->CCR = DMA_CCR_TCIE | DMA_CCR_EN;
 }
 
-constexpr const uint32_t UART4_RX_BUFFER_SIZE = 1024;
-uint8_t uart4_receive_buffer[UART4_RX_BUFFER_SIZE];
-
-void
-uart4_receive_to_idle()
-{
-  UART4->ICR |= USART_ICR_IDLECF;
-  GPDMA1_Channel1->CBR1 = UART4_RX_BUFFER_SIZE;
-  GPDMA1_Channel1->CDAR = (uint32_t) uart4_receive_buffer;
-  GPDMA1_Channel1->CSAR = (uint32_t) &UART4->RDR;
-  GPDMA1_Channel1->CCR = DMA_CCR_EN;
-}
+// void
+// uart4_receive_to_idle()
+// {
+//   UART4->ICR |= USART_ICR_IDLECF;
+//   GPDMA1_Channel1->CBR1 = Uart4::RX_BUFFER_SIZE;
+//   GPDMA1_Channel1->CDAR = (uint32_t) uart4_receive_buffer;
+//   GPDMA1_Channel1->CSAR = (uint32_t) &UART4->RDR;
+//   GPDMA1_Channel1->CCR = DMA_CCR_EN;
+// }
 
 void
 uart4_setup()
@@ -70,8 +120,29 @@ uart4_setup()
   UART4->ICR |= USART_ICR_IDLECF;
   NVIC_SetPriority(UART4_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 1, 2));
   NVIC_EnableIRQ(UART4_IRQn);
+
+  // uart4_receive_to_idle();
 }
 
+// void
+// __uart4_received_message(uint8_t* cstr)
+// {
+//   if (queue.size() >= max_messages_no)
+//     return;
+//   queue.push((const char*) cstr);
+// }
+
+// bool
+// uart4_data_received(etl::string<UART4_RX_BUFFER_SIZE + 1>& str)
+// {
+//   if (queue.empty())
+//     return false;
+//   //	str = std::move(queue.front());
+//   queue.pop_into(str);
+//   return true;
+//   //	return queue.front();
+// }
+
 void
 uart6_setup()
 {