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87 changes: 86 additions & 1 deletion README.md
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Original file line number Diff line number Diff line change
@@ -1,4 +1,4 @@
# Counter_4bit_up-down
![Untitled](https://github.com/user-attachments/assets/2099f96d-144e-4e3a-820e-aa9727b45f9f)# Counter_4bit_up-down

## Aim:

Expand Down Expand Up @@ -42,6 +42,7 @@ Functional Simulation:

 After this you can see the window like below

![Untitled](https://github.com/user-attachments/assets/c1739b3f-2d83-4cb1-8199-10f10c8d1a30)

## Fig 2: Invoke the Cadence Environment

Expand All @@ -58,6 +59,32 @@ Functional Simulation:

*/Program for 4-Bit Up-Down Counter

timescale Ins / 1 ns

module counter(clk,m,rst,count);

input clk.m.rst;

output reg [3:0] count;

always@(posedge clk or negedge rst)

begin

if (!rst)

count=0; else if(m)

count=count+1;

else

count=count-1;

end

endmodule

 Use Save option or Ctrl+S to save the code or click on the save option from the top most right corner and close the text file.

## Creating Test bench:
Expand All @@ -68,19 +95,61 @@ Functional Simulation:

*/Test bench Program for 4-Bit Up-Down Counter

`timescale 1ns/1ns

module counter_test; reg clk,rst,m;

wire [3:0] count; initial

begin

clk=0;

rst=0;#5; rst=1;

end

initial

begin

m=1;

#160 m=0;

end

counter counter1 (clk.m.rst, count);

always #5 clk=-clk;

initial Smonitor("Time=%t rst-%b clk=%b count=%b", $time,rst,clk,count);

initial

#320 Sfinish:

endmodule

### To Launch Simulation tool
 linux:/> nclaunch -new& // “-new” option is used for invoking NCVERILOG for the first time for any design

 linux:/> nclaunch& // On subsequent calls to NCVERILOG

It will invoke the nclaunch window for functional simulation we can compile,elaborate and simulate it using Multiple step


![Untitled](https://github.com/user-attachments/assets/d55520d3-7380-4245-a8b9-673bb22fae1c)


## Fig 3: Setting Multi-step simulation

Select Multiple Step and then select “Create cds.lib File” as shown in below figure

Click the cds.lib file and save the file by clicking on Save option

![Untitled-1](https://github.com/user-attachments/assets/39c1b585-c84c-403d-b566-f2222a7deffc)

## Fig 4: cds.lib file Creation

 Save cds.lib file and select the correct option for cds.lib file format based on the HDL Language and Libraries used.
Expand All @@ -89,6 +158,8 @@ Click the cds.lib file and save the file by clicking on Save option

 We are simulating verilog design without using any libraries

![Untitled-1](https://github.com/user-attachments/assets/61639793-a24b-4843-818d-f963d229bbc9)

## Fig 5: Selection of Don’t include any libraries

 A Click “OK” in the “nclaunch: Open Design Directory” window
Expand All @@ -99,6 +170,9 @@ Click the cds.lib file and save the file by clicking on Save option

 Worklib is the directory where all the compiled codes are stored while Snapshot will have output of elaboration which in turn goes for simulation

![Untitled](https://github.com/user-attachments/assets/9e86f803-87f2-4ac7-a814-5c40ffb49031)


## Fig 6: Nclaunch Window

To perform the function simulation, the following three steps are involved Compilation, Elaboration and Simulation.
Expand All @@ -123,6 +197,8 @@ i.e Cadence IES command for compile: ncverilog +access+rwc -compile fa.v

Worklib is the directory where all the compiled codes are stored while Snapshot will have output of elaboration which in turn goes for simulation

![Untitled-1](https://github.com/user-attachments/assets/10282ced-aa92-4a12-84ef-20ca78859189)

## Fig 7: Compiled database in worklib

 After compilation it will come under worklib you can see in right side window
Expand Down Expand Up @@ -152,6 +228,9 @@ It contains statements that map logical library names to their physical director

 After elaboration the file will come under snapshot. Select the test bench and simulate it.

![Untitled](https://github.com/user-attachments/assets/4fb7a53d-d27c-4a79-8a71-0b81d6c37fcc)


## Fig 8: Elaboration Launch Option

### Step 3: Simulation: – Simulate with the given test vectors over a period of time to observe the output behaviour.
Expand All @@ -164,10 +243,16 @@ It contains statements that map logical library names to their physical director

 Steps for simulation – Run the simulation command with simulator options


![Untitled](https://github.com/user-attachments/assets/6d068d14-92d2-479d-b516-ad54bd11ff9b)

## Fig 9: Design Browser window for simulation
![Untitled-1](https://github.com/user-attachments/assets/ed3e0428-f8ac-4a89-825f-d3c593efb742)

## Fig 10: Simulation Waveform Window

![Untitled](https://github.com/user-attachments/assets/e3ab2aef-8789-4e3a-9065-c962cdb6bec7)

## Fig 11: Simulation Waveform Window

### Result
Expand Down