Update README.md

README.md

@@ -41,6 +41,7 @@ Functional Simulation:
       (The path of cshrc could vary depending on the installation destination)
 
 	After this you can see the window like below 
+![Screenshot 2024-11-08 101603](https://github.com/user-attachments/assets/1e47e7c5-1104-4638-928e-3136572a60b2)
 
 
 ## Fig 2: Invoke the Cadence Environment
@@ -74,12 +75,14 @@ Functional Simulation:
 	linux:/> nclaunch&                 // On subsequent calls to NCVERILOG
 
 It will invoke the nclaunch window for functional simulation we can compile,elaborate and simulate it using Multiple step
+![Screenshot 2024-11-08 100827](https://github.com/user-attachments/assets/d2385140-6753-4d68-9744-dcd0e1e6c612)
 
 ## Fig 3: Setting Multi-step simulation
 
 Select Multiple Step and then select “Create cds.lib File” as shown in below figure
 
 Click the cds.lib file and save the file by clicking on Save option
+![Screenshot 2024-11-08 100837](https://github.com/user-attachments/assets/e7e233a1-3473-47a1-9f05-3dedbd0cfcd5)
 
 ## Fig 4: cds.lib file Creation
 
@@ -88,6 +91,7 @@ Click the cds.lib file and save the file by clicking on Save option
 	Select “Don’t include any libraries (verilog design)” from “New cds.lib file” and click on “OK” as in below figure
 
 	We are simulating verilog design without using any libraries
+![Screenshot 2024-11-08 100837](https://github.com/user-attachments/assets/b8a5df07-9627-43d9-8778-df1ca07cb2f8)
 
 ## Fig 5: Selection of Don’t include any libraries
 
@@ -98,6 +102,7 @@ Click the cds.lib file and save the file by clicking on Save option
 	Left side you can see the HDL files. Right side of the window has worklib and snapshots directories listed.
 
 	Worklib is the directory where all the compiled codes are stored while Snapshot will have output of elaboration which in turn goes for simulation
+![Screenshot 2024-11-08 100935](https://github.com/user-attachments/assets/455d0cf0-1162-42af-a724-605077afc633)
 
 ## Fig 6: Nclaunch Window
 
@@ -122,6 +127,7 @@ i.e Cadence IES command for compile: ncverilog +access+rwc -compile fa.v
 Left side select the file and in Tools : launch verilog compiler with current selection will get enable. Click it to compile the code 
 
 Worklib is the directory where all the compiled codes are stored while Snapshot will have output of elaboration which in turn goes for simulation 
+![Screenshot 2024-11-08 101030](https://github.com/user-attachments/assets/6ed74a94-94fe-4a40-8675-8bc4478866f2)
 
 ## Fig 7: Compiled database in worklib
 
@@ -151,6 +157,7 @@ It contains statements that map logical library names to their physical director
 9.	It also establishes net connectivity and prepares all of this for simulation
 
 	After elaboration the file will come under snapshot. Select the test bench and simulate it. 
+![Screenshot 2024-11-08 101030](https://github.com/user-attachments/assets/297ed180-3ede-4975-8cf2-2b1472553f3b)
 
 ## Fig 8: Elaboration Launch Option
 
@@ -163,10 +170,14 @@ It contains statements that map logical library names to their physical director
 	Simulation allow to dump design and test bench signals into a waveform 
 
 	Steps for simulation – Run the simulation command with simulator options
+![Screenshot 2024-11-08 101135](https://github.com/user-attachments/assets/4ef04ff6-9986-4ae0-b010-ab760fb9bc2f)
 
 ## Fig 9: Design Browser window for simulation
+![Screenshot 2024-11-08 101217](https://github.com/user-attachments/assets/8a267d0d-87c3-4789-b3c5-96bd2687d962)
 
 ## Fig 10: Simulation Waveform Window
 
+![Screenshot 2024-11-08 101312](https://github.com/user-attachments/assets/5d144c44-4e13-49c8-93e1-65b985b983f9)
+
 ## Fig 11: Simulation Waveform Window