Update README.md

README.md

@@ -53,10 +53,48 @@ Note : File name should be with HDL Extension
 
 •	fa.v → Single Bit 3-Input Full Adder [Sub-Module / Function] 
 
+CODE:
+   module full adder(A,B,CIN,S.COUT);
+   input A,B,CIN;
+   output S,COUT;
+   assign
+   S=A^BACIN;
+   assign COUT=(A&B) | (CIN&(A^B)); endmodule
+
 •	fa_4bit.v → Top Module for Adding 4-bit Inputs. 
 
+CODE:
+module fulladd_4bit(A,B,CO,S,C4); input
+[3:0] Α.Β;
+input CO; output [3:0] S; output C4:
+wire C1,C2,C3;
+full_adder fa0 (A[0],B[0],CO,S[0],C1);
+full_adder fal (A[1], B[1],C1.S[1],C2);
+full_adder fa2 (A[2],B[2],C2,S[2],C3);
+full_adder fa3 (A[3],B[3],C3,S[3],C4);
+endmodule
+
 •	fa_4bit_test.v → Test bench 
 
+CODE:
+module test_4bit;
+reg [3:0] A;
+reg [3:0] B; reg CO; wire
+[3:0] S; wire C4: module
+test 4bit;
+reg [3:0] A;
+reg [3:0] B; reg CO; wire
+[3:0] S; wire C4;
+fulladd 4bit dut (A,B,CO,S,C4); initial
+begin
+A=460011;B-460011;C0=160;
+#10; A-461011;B=460111;C0-161;
+#10; A-4b1111;B=4b1111;C0-161;
+#10;
+end initial
+#50 Sfinish:
+endmodule
+
 */Program to design 4 bit adder by instantiating 1 bit Full adder.also add test bench program */
 Developed by: Register Number*/
 
@@ -70,6 +108,9 @@ Developed by: Register Number*/
 
       (The path of cshrc could vary depending on the installation destination)
 
+   ![Untitled](https://github.com/user-attachments/assets/4f88dcfc-169b-4963-8bb6-3e8040c39625)
+
+
 	After this you can see the window like below 
 
 ### Fig 3:Invoke the Cadence Environment
@@ -83,12 +124,16 @@ or
 •	linux:/> nclaunch& // On subsequent calls to NCVERILOG 
 
 	It will invoke the nclaunch window for functional simulation we can compile,elaborate and simulate it using Multiple Step .
+![Untitled](https://github.com/user-attachments/assets/07274bfc-4f86-4d0f-8a64-c9abf8ded738)
+
 
 ### Fig 4:Setting Multi-step simulation
 
 	Select Multiple Step and then select “Create cds.lib File” .
 
 	Click the cds.lib file and save the file by clicking on Save option 
+![Untitled-1](https://github.com/user-attachments/assets/0bd11bb2-d7e1-4261-8c29-fa947f7a33eb)
+
 
 ### Fig 5:cds.lib file Creation
 
@@ -113,6 +158,9 @@ or
 	To perform the function simulation, the following three steps are involved Compilation, Elaboration and Simulation. 
 
 ### Fig 7: Nclaunch Window
+![Untitled](https://github.com/user-attachments/assets/6c299247-0f55-469d-866a-c6360d0464e3)
+
+
 
 ## Step 1: Compilation:– Process to check the correct Verilog language syntax and usage 
 
@@ -126,6 +174,9 @@ or
 2. Map the work to library created (most of the latest simulation tools creates automatically) 
 3. Run the compile command with compile options 
 i.e Cadence IES command for compile: ncverilog +access+rwc -compile fa.v
+![Untitled-1](https://github.com/user-attachments/assets/0e1c25b3-33eb-418e-a37c-43f1cebf28b9)
+
+
 
 Left side select the file and in Tools : launch verilog compiler with current selection will get enable. Click it to compile the code 
 
@@ -155,6 +206,8 @@ i.e Cadence IES command for compile: ncverilog +access+rwc -compile fa.v
 	After elaboration the file will come under snapshot. Select the test bench and elaborate it.
 
 ### Fig 9: Elaboration Launch Option
+![Untitled](https://github.com/user-attachments/assets/a12caf19-7766-46e1-b09c-9aa96edc4e3a)
+
 
 ## Step 3: Simulation: – Simulate with the given test vectors over a period of time to observe the output behaviour. 
 
@@ -167,10 +220,18 @@ i.e Cadence IES command for compile: ncverilog +access+rwc -compile fa.v
 	Steps for simulation – Run the simulation command with simulator options
 
 ### Fig 10: Design Browser window for simulation
+![Untitled](https://github.com/user-attachments/assets/3623c714-bda8-4117-9150-ea383f69f5b0)
+
 
 ### Fig 11: Launching Simulation Waveform WindowSimulation Waveform Window
+![Untitled](https://github.com/user-attachments/assets/9110214c-b00b-43e3-aaed-f51e8c7fff44)
+
+
 
 ### Fig 12: Simulation Waveform Window
+![Untitled](https://github.com/user-attachments/assets/a2dcef28-3888-4bdc-bb9c-1f00c60b9527)
+
+
 
 ### Result: