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91 changes: 83 additions & 8 deletions README.md
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Original file line number Diff line number Diff line change
Expand Up @@ -57,10 +57,76 @@ Note : File name should be with HDL Extension

• fa_4bit_test.v → Test bench

*/Program to design 4 bit adder by instantiating 1 bit Full adder.also add test bench program */
Developed by: Register Number*/
## full_adder_code
```
module full_adder(A,B,CIN,S,COUT);

## Functional Simulation:
input A,B,CIN;

output S,COUT;

assign S=A^B^CIN;

assign COUT=(A&B) | (CIN&(A^B));

endmodule
```

## full_add_4bit
```
module fulladd_4bit(A,B,C0,S,C4);

input [3:0] A,B;

input C0;

output [3:0] S;

output C4;

wire C1,C2,C3;

full_adder fa0 (A[0],B[0],C0,S[0],C1);

full_adder fa1 (A[1],B[1],C1,S[1],C2);

full_adder fa2 (A[2],B[2],C2,S[2],C3);

full_adder fa3 (A[3],B[3],C3,S[3],C4);

endmodule
```

## full_add_4bit_test
```
module test_4bit;

reg [3:0] A;

reg [3:0] B; reg C0;

wire [3:0] S; wire C4;

fulladd_4bit dut (A,B,C0,S,C4);

initial

begin

A=4'b0011;B=4'b0011;C0=1'b0;

#10; A=4'b1011;B=4'b0111;C0=1'b1;

#10; A=4'b1111;B=4'b1111;C0=1'b1;

#10;

end initial

#50 $finish;
endmodule
```
### Functional Simulation:

 Invoke the cadence environment by type the below commands

Expand All @@ -71,9 +137,12 @@ Developed by: Register Number*/
(The path of cshrc could vary depending on the installation destination)

 After this you can see the window like below
![Screenshot 2024-11-25 100733](https://github.com/user-attachments/assets/d08325ca-ad6d-4fa2-805d-008df61c9bb1)


### Fig 3:Invoke the Cadence Environment


 To Launch Simulation tool

• linux:/> nclaunch -new& // “-new” option is used for invoking NCVERILOG for the first time for any design
Expand All @@ -83,13 +152,16 @@ or
• linux:/> nclaunch& // On subsequent calls to NCVERILOG

 It will invoke the nclaunch window for functional simulation we can compile,elaborate and simulate it using Multiple Step .
![Screenshot 2024-11-25 100817](https://github.com/user-attachments/assets/5bddaaee-6143-453b-9683-c15026f94615)

### Fig 4:Setting Multi-step simulation

 Select Multiple Step and then select “Create cds.lib File” .

 Click the cds.lib file and save the file by clicking on Save option

![Screenshot 2024-10-02 101402](https://github.com/user-attachments/assets/1a66ef0e-4af3-4de2-8725-a53fd5ee6146)

### Fig 5:cds.lib file Creation

 Save cds.lib file and select the correct option for cds.lib file format based on the HDL Language and Libraries used.
Expand All @@ -100,7 +172,7 @@ or

• A Click “OK” in the “nclaunch: Open Design Directory” window as shown in below figure

![image](https://github.com/user-attachments/assets/781b297a-11e9-4140-89c5-ee3b0d15bbd4)
![Screenshot 2024-11-25 101002](https://github.com/user-attachments/assets/3c8bdfa7-bd41-4ef2-84d3-12a8e886c641)

### Fig 6: Selection of Don’t include any libraries

Expand All @@ -114,6 +186,7 @@ or

### Fig 7: Nclaunch Window


## Step 1: Compilation:– Process to check the correct Verilog language syntax and usage

 Inputs: Supplied are Verilog design and test bench codes
Expand All @@ -138,6 +211,8 @@ i.e Cadence IES command for compile: ncverilog +access+rwc -compile fa.v
 Select the test bench and compile it. It will come under worklib. Under Worklib you can see the module and test-bench.

 The cds.lib file is an ASCII text file. It defines which libraries are accessible and where they are located. It contains statements that map logical library names to their physical directory paths. For this Design, you will define a library called “worklib”
![Screenshot 2024-11-25 101219](https://github.com/user-attachments/assets/fc700ab5-6705-4562-9295-300fb39d82be)


## Step 2: Elaboration:– To check the port connections in hierarchical design
 Inputs: Top level design / test bench Verilog codes
Expand All @@ -153,6 +228,7 @@ i.e Cadence IES command for compile: ncverilog +access+rwc -compile fa.v
5. It also establishes net connectivity and prepares all of this for simulation

 After elaboration the file will come under snapshot. Select the test bench and elaborate it.
![Screenshot 2024-10-02 104200](https://github.com/user-attachments/assets/b06332b7-31ca-4c88-badd-c4cb086f5a81)

### Fig 9: Elaboration Launch Option

Expand All @@ -167,14 +243,13 @@ i.e Cadence IES command for compile: ncverilog +access+rwc -compile fa.v
 Steps for simulation – Run the simulation command with simulator options

### Fig 10: Design Browser window for simulation

![Screenshot 2024-10-02 101646](https://github.com/user-attachments/assets/8edd4bde-6e23-4db1-ad15-50feefcdd0bc)
### Fig 11: Launching Simulation Waveform WindowSimulation Waveform Window

![Screenshot 2024-10-02 101735](https://github.com/user-attachments/assets/2945e527-c7f2-46bc-b2b1-a362290e39bd)
### Fig 12: Simulation Waveform Window
![Screenshot 2024-10-02 101833](https://github.com/user-attachments/assets/b4d6c582-962d-4d87-995e-2743bf9ed129)

### Result:

The functionality of a 4-bit adder was successfully verified using a test bench and simulated with the nclaunch tool.



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