Skip to content

Commit

Permalink
More modifications to general FPGA timing
Browse files Browse the repository at this point in the history
  • Loading branch information
@rodmarfran
rodmarfran committed May 11, 2021
1 parent 60426b7 commit 2f23dbd
Show file tree
Hide file tree
Showing 28 changed files with 5,848 additions and 394 deletions.
4 changes: 2 additions & 2 deletions G3U_HW_V02_2GB/Qsys_Project/software/Simucam_R0_UART_bsp/settings.bsp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -2,8 +2,8 @@
<sch:Settings xmlns:sch="http://www.altera.com/embeddedsw/bsp/schema">
<BspType>ucosii</BspType>
<BspVersion>18.1</BspVersion>
<BspGeneratedTimeStamp>May 5, 2021 8:13:42 AM</BspGeneratedTimeStamp>
<BspGeneratedUnixTimeStamp>1620213222316</BspGeneratedUnixTimeStamp>
<BspGeneratedTimeStamp>May 6, 2021 9:01:16 AM</BspGeneratedTimeStamp>
<BspGeneratedUnixTimeStamp>1620302476542</BspGeneratedUnixTimeStamp>
<BspGeneratedLocation>.\</BspGeneratedLocation>
<BspSettingsFile>settings.bsp</BspSettingsFile>
<SopcDesignFile>..\..\MebX_Qsys_Project.sopcinfo</SopcDesignFile>
Expand Down
4 changes: 2 additions & 2 deletions G3U_HW_V02_2GB/Qsys_Project/software/Simucam_R0_UART_bsp/summary.html
View file
Original file line number Diff line number Diff line change
Expand Up @@ -22,10 +22,10 @@ <h3>BSP Description</h3>
<td width="20%" bgcolor="#77BBFF">BSP Version:</td><td>18.1</td>
</tr>
<tr mode="wrap">
<td width="20%" bgcolor="#77BBFF">BSP Generated On:</td><td>May 5, 2021 8:13:42 AM</td>
<td width="20%" bgcolor="#77BBFF">BSP Generated On:</td><td>May 6, 2021 9:01:16 AM</td>
</tr>
<tr mode="wrap">
<td width="20%" bgcolor="#77BBFF">BSP Generated Timestamp:</td><td>1620213222316</td>
<td width="20%" bgcolor="#77BBFF">BSP Generated Timestamp:</td><td>1620302476542</td>
</tr>
<tr mode="wrap">
<td width="20%" bgcolor="#77BBFF">BSP Generated Location:</td><td>.\</td>
Expand Down
32 changes: 16 additions & 16 deletions G3U_HW_V02_2GB/Quartus_Project/MebX_Qsys_Project_m1_ddr2_memory_p0_summary.csv
View file
Original file line number Diff line number Diff line change
@@ -1,29 +1,29 @@
Core: MebX_Qsys_Project_m1_ddr2_memory_p0 - Instance: SOPC_INST|m1_ddr2_memory
Path, Setup Margin, Hold Margin
"Address Command (Slow 900mV 85C Model)",0.193,0.589
"Bus Turnaround Time (Slow 900mV 85C Model)",5.445,--
"Core (Slow 900mV 85C Model)",0.156,-0.019
"Core Recovery/Removal (Slow 900mV 85C Model)",0.553,0.519
"Address Command (Slow 900mV 85C Model)",0.192,0.587
"Bus Turnaround Time (Slow 900mV 85C Model)",5.441,--
"Core (Slow 900mV 85C Model)",0.392,-0.028
"Core Recovery/Removal (Slow 900mV 85C Model)",0.67,0.462
"Read Capture (Slow 900mV 85C Model)",0.15,0.102
"Read Resync (Slow 900mV 85C Model)",2.405,5.256
"Read Resync (Slow 900mV 85C Model)",2.603,5.335
"Write (Slow 900mV 85C Model)",-0.084,-0.084
"Write Leveling tDQSS (Slow 900mV 85C Model)",0.392,0.392
"Write Leveling tDSS/tDSH (Slow 900mV 85C Model)",0.42,0.42
"Address Command (Slow 900mV 0C Model)",0.181,0.646
"Bus Turnaround Time (Slow 900mV 0C Model)",5.473,--
"Core (Slow 900mV 0C Model)",0.39,0.042
"Core Recovery/Removal (Slow 900mV 0C Model)",0.856,0.5
"Address Command (Slow 900mV 0C Model)",0.178,0.644
"Bus Turnaround Time (Slow 900mV 0C Model)",5.467,--
"Core (Slow 900mV 0C Model)",0.618,0.032
"Core Recovery/Removal (Slow 900mV 0C Model)",0.874,0.452
"Read Capture (Slow 900mV 0C Model)",0.152,0.104
"Read Resync (Slow 900mV 0C Model)",2.452,5.354
"Read Resync (Slow 900mV 0C Model)",2.651,5.392
"Write (Slow 900mV 0C Model)",-0.054,-0.054
"Write Leveling tDQSS (Slow 900mV 0C Model)",0.392,0.392
"Write Leveling tDSS/tDSH (Slow 900mV 0C Model)",0.42,0.42
"Address Command (Fast 900mV 0C Model)",0.135,0.829
"Bus Turnaround Time (Fast 900mV 0C Model)",5.515,--
"Core (Fast 900mV 0C Model)",0.655,0.139
"Core Recovery/Removal (Fast 900mV 0C Model)",2.422,0.269
"Address Command (Fast 900mV 0C Model)",0.134,0.828
"Bus Turnaround Time (Fast 900mV 0C Model)",5.513,--
"Core (Fast 900mV 0C Model)",0.607,0.143
"Core Recovery/Removal (Fast 900mV 0C Model)",2.368,0.253
"Read Capture (Fast 900mV 0C Model)",0.182,0.134
"Read Resync (Fast 900mV 0C Model)",3.08,5.757
"Write (Fast 900mV 0C Model)",-0.07,-0.07
"Read Resync (Fast 900mV 0C Model)",3.216,5.802
"Write (Fast 900mV 0C Model)",-0.072,-0.072
"Write Leveling tDQSS (Fast 900mV 0C Model)",0.392,0.392
"Write Leveling tDSS/tDSH (Fast 900mV 0C Model)",0.42,0.42
24 changes: 12 additions & 12 deletions G3U_HW_V02_2GB/Quartus_Project/MebX_Qsys_Project_m2_ddr2_memory_p0_summary.csv
View file
Original file line number Diff line number Diff line change
@@ -1,29 +1,29 @@
Core: MebX_Qsys_Project_m2_ddr2_memory_p0 - Instance: SOPC_INST|m2_ddr2_memory
Path, Setup Margin, Hold Margin
"Address Command (Slow 900mV 85C Model)",0.177,0.578
"Bus Turnaround Time (Slow 900mV 85C Model)",5.428,--
"Core (Slow 900mV 85C Model)",0.0,0.168
"Core Recovery/Removal (Slow 900mV 85C Model)",0.487,0.515
"Read Capture (Slow 900mV 85C Model)",0.149,0.101
"Read Resync (Slow 900mV 85C Model)",2.817,5.267
"Address Command (Slow 900mV 85C Model)",0.177,0.574
"Bus Turnaround Time (Slow 900mV 85C Model)",5.429,--
"Core (Slow 900mV 85C Model)",0.196,0.099
"Core Recovery/Removal (Slow 900mV 85C Model)",0.557,0.519
"Read Capture (Slow 900mV 85C Model)",0.15,0.102
"Read Resync (Slow 900mV 85C Model)",2.792,5.293
"Write (Slow 900mV 85C Model)",-0.084,-0.084
"Write Leveling tDQSS (Slow 900mV 85C Model)",0.392,0.392
"Write Leveling tDSS/tDSH (Slow 900mV 85C Model)",0.42,0.42
"Address Command (Slow 900mV 0C Model)",0.16,0.647
"Bus Turnaround Time (Slow 900mV 0C Model)",5.465,--
"Core (Slow 900mV 0C Model)",0.287,0.268
"Core Recovery/Removal (Slow 900mV 0C Model)",0.769,0.497
"Core (Slow 900mV 0C Model)",0.411,0.225
"Core Recovery/Removal (Slow 900mV 0C Model)",0.67,0.499
"Read Capture (Slow 900mV 0C Model)",0.152,0.104
"Read Resync (Slow 900mV 0C Model)",2.865,5.306
"Read Resync (Slow 900mV 0C Model)",2.871,5.416
"Write (Slow 900mV 0C Model)",-0.055,-0.055
"Write Leveling tDQSS (Slow 900mV 0C Model)",0.392,0.392
"Write Leveling tDSS/tDSH (Slow 900mV 0C Model)",0.42,0.42
"Address Command (Fast 900mV 0C Model)",0.128,0.831
"Bus Turnaround Time (Fast 900mV 0C Model)",5.518,--
"Core (Fast 900mV 0C Model)",0.64,0.121
"Core Recovery/Removal (Fast 900mV 0C Model)",2.383,0.271
"Core (Fast 900mV 0C Model)",0.645,0.125
"Core Recovery/Removal (Fast 900mV 0C Model)",2.071,0.268
"Read Capture (Fast 900mV 0C Model)",0.182,0.134
"Read Resync (Fast 900mV 0C Model)",3.328,5.759
"Read Resync (Fast 900mV 0C Model)",3.285,5.724
"Write (Fast 900mV 0C Model)",-0.075,-0.075
"Write Leveling tDQSS (Fast 900mV 0C Model)",0.392,0.392
"Write Leveling tDSS/tDSH (Fast 900mV 0C Model)",0.42,0.42
Loading

0 comments on commit 2f23dbd

Please sign in to comment.