Popular repositories Loading

1. PresentationDeckAssistant PresentationDeckAssistant Public

   TypeScript

2. sync-fifo-dv sync-fifo-dv Public

   Parameterized synchronous FIFO design and verification in SystemVerilog

   SystemVerilog

3. serial-zynq-peripheral serial-zynq-peripheral Public

   SystemVerilog

4. tinynpu-rtl-to-gds tinynpu-rtl-to-gds Public

   FPGA SoC project with a verified INT8 TinyNPU accelerator and a pipelined RV32I CPU, UART, VGA, verification, and ASIC flow in development.

   SystemVerilog