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Buffer handling overhaul, remove fixed packet length in favour if var…
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…iable length
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@LouDnl
LouDnl committed Jan 22, 2025
1 parent 28f1713 commit 42aa657
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Showing 6 changed files with 201 additions and 161 deletions.
38 changes: 27 additions & 11 deletions src/globals.h
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Original file line number Diff line number Diff line change
Expand Up @@ -41,17 +41,33 @@
/* USBSID command byte */
enum
{
WRITE = 0, /* 0 */
READ, /* 1 */
PAUSE, /* 2 */
RESET_SID, /* 3 */
DISABLE_SID, /* 4 */
ENABLE_SID, /* 5 */
CLEAR_BUS, /* 6 */
RESET_MCU, /* 7 */
BOOTLOADER, /* 8 */
MUTE, /* 9 */
UNMUTE, /* 10 */
PACKET_TYPE = 0xC0, /* 0b11000000 ~ 192 */
BYTE_MASK = 0x3F, /* 0b111111 ~ 63 */
COMMAND_MASK = 0x1F, /* 0b11111 ~ 31 */

/* BYTE 0 */
/* Top 2 bits */
WRITE = 0, /* 0b0 ~ 0x00 */
READ = 1, /* 0b1 ~ 0x40 */
CYCLED_WRITE = 2, /* 0b10 ~ 0x80 */
COMMAND = 3, /* 0b11 ~ 0xC0 */
/* Lower 6 bits for byte count */
/* Lower 6 bits for Commands */
PAUSE = 10, /* 0b1010 ~ 0x0A */
UNPAUSE = 11, /* 0b1011 ~ 0x0B */
MUTE = 12, /* 0b1100 ~ 0x0C */
UNMUTE = 13, /* 0b1101 ~ 0x0D */
RESET_SID = 14, /* 0b1110 ~ 0x0E */
DISABLE_SID = 15, /* 0b1111 ~ 0x0F */
ENABLE_SID = 16, /* 0b10000 ~ 0x10 */
CLEAR_BUS = 17, /* 0b10001 ~ 0x11 */
CONFIG = 18, /* 0b10010 ~ 0x12 */
RESET_MCU = 19, /* 0b10011 ~ 0x13 */
BOOTLOADER = 20, /* 0b10100 ~ 0x14 */

/* GPIO COMMANDS */
G_PAUSE = 2,
G_CLEAR_BUS = 3,
};

/* USB data type */
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28 changes: 22 additions & 6 deletions src/gpio.c
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Original file line number Diff line number Diff line change
Expand Up @@ -303,11 +303,11 @@ uint8_t __not_in_flash_func(bus_operation)(uint8_t command, uint8_t address, uin
pio_sm_exec(bus_pio, sm_control, pio_encode_irq_set(false, 4)); /* Preset the statemachine IRQ to not wait for a 1 */
pio_sm_exec(bus_pio, sm_data, pio_encode_irq_set(false, 5)); /* Preset the statemachine IRQ to not wait for a 1 */
switch (command & 0x0F) {
case PAUSE:
case G_PAUSE:
control_word = 0b110110;
dma_channel_set_read_addr(dma_tx_control, &control_word, true); /* Control lines RW, CS1 & CS2 DMA transfer */
break;
case CLEAR_BUS:
case G_CLEAR_BUS:
dir_mask = 0b1111111111111111;
data_word = (dir_mask << 16) | 0x0;
dma_channel_set_read_addr(dma_tx_data, &data_word, true); /* Data & Address DMA transfer */
Expand Down Expand Up @@ -350,12 +350,12 @@ uint8_t __not_in_flash_func(bus_operation)(uint8_t command, uint8_t address, uin
dma_channel_wait_for_finish_blocking(dma_rx_data);
GPIODBG("[R]$%08x 0b"PRINTF_BINARY_PATTERN_INT32" $%04x 0b"PRINTF_BINARY_PATTERN_INT16"\r\n", read_data, PRINTF_BYTE_TO_BINARY_INT32(read_data), control_word, PRINTF_BYTE_TO_BINARY_INT16(control_word));
return (read_data >> 24) & 0xFF;
case PAUSE:
case G_PAUSE:
case WRITE:
dma_channel_wait_for_finish_blocking(dma_tx_control);
GPIODBG("[W]$%08x 0b"PRINTF_BINARY_PATTERN_INT32" $%04x 0b"PRINTF_BINARY_PATTERN_INT16"\r\n", data_word, PRINTF_BYTE_TO_BINARY_INT32(data_word), control_word, PRINTF_BYTE_TO_BINARY_INT16(control_word));
return 0;
case CLEAR_BUS:
case G_CLEAR_BUS:
/* don't wait, just fall through */
default:
return 0;
Expand Down Expand Up @@ -399,18 +399,24 @@ void __not_in_flash_func(cycled_bus_operation)(uint8_t address, uint8_t data, ui

void unmute_sid(void)
{
DBG("[UNMUTE] ");
for (int i = 0; i < numsids; i++) {
if ((volume_state[i] & 0xF) == 0) volume_state[i] = (volume_state[i] & 0xF0) | 0x0E;
bus_operation((0x10 | WRITE), ((0x20 * i) + 0x18), volume_state[i]); /* Volume back */
DBG("[%d] 0x%02X ", i, volume_state[i]);
}
DBG("\n");
}

void mute_sid(void)
{
DBG("[MUTE] ");
for (int i = 0; i < numsids; i++) {
volume_state[i] = sid_memory[((0x20 * i) + 0x18)];
bus_operation((0x10 | WRITE), ((0x20 * i) + 0x18), (volume_state[i] & 0xF0)); /* Volume to 0 */
DBG("[%d] 0x%02X ", i, volume_state[i]);
}
DBG("\n");
}

void enable_sid(void)
Expand All @@ -431,15 +437,22 @@ void disable_sid(void)

void clear_bus(void)
{
bus_operation((0x10 | CLEAR_BUS), 0x0, 0x0);
bus_operation((0x10 | G_CLEAR_BUS), 0x0, 0x0);
}

void pause_sid(void)
{
bus_operation((0x10 | G_PAUSE), 0x0, 0x0);
}

void pause_sid_withmute(void)
{
DBG("[PAUSE STATE PRE] %d\n", paused_state);
if (paused_state == 0) mute_sid();
if (paused_state == 1) unmute_sid();
bus_operation((0x10 | PAUSE), 0x0, 0x0);
bus_operation((0x10 | G_PAUSE), 0x0, 0x0);
paused_state = !paused_state;
DBG("[PAUSE STATE POST] %d\n", paused_state);
}

void reset_sid(void)
Expand All @@ -453,6 +466,9 @@ void reset_sid(void)

void reset_sid_registers(void)
{
paused_state = 0;
gpio_put(CS1, 1);
gpio_put(CS2, 1);
gpio_put(RES, 0);
sleep_us(10);
gpio_put(RES, 1);
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39 changes: 18 additions & 21 deletions src/pio/bus_control.pio
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Original file line number Diff line number Diff line change
Expand Up @@ -46,43 +46,40 @@

; Delay counter program
.program delay_timer
.side_set 1 opt
.wrap_target
pull block side 1 ; Pull data from FIFO
out x 16 side 1 ; Move data into scratch register x
pull block ; Pull data from FIFO
out x 16 ; Move data into scratch register x
delay:
wait 1 gpio PHI side 1 ; Wait for clock to go high
wait 0 gpio PHI side 0 ; Wait for clock to go low
wait 1 gpio PHI ; Wait for clock to go high
wait 0 gpio PHI ; Wait for clock to go low
jmp x-- delay ; Decrease x and restart count
irq set BUSIRQ side 0 ; Set IRQ and continue
irq wait DATAIRQ side 0 ; Set IRQ and wait for its release
irq set BUSIRQ ; Set IRQ and continue
irq wait DATAIRQ ; Set IRQ and wait for its release
.wrap

; Bus control program
.program bus_control
.wrap_target
pull block ; Pull data from FIFO
wait 1 irq BUSIRQ ; Wait for IRQ signal
; wait 1 gpio PHI ; Wait for clock to go high ; ISSUE: For async this is shit, for sync this is great
wait 0 gpio PHI [26] ; Wait for clock to go low
out pins, 3 ; Set control pins (19-21)
wait 1 gpio PHI [24] ; Wait for clock to go high
jmp pin read ; Jump to read if IN pin is high
jmp done ; Jump to done if write and wait
pull block ; Pull data from FIFO
wait 1 irq BUSIRQ ; Wait for IRQ signal
wait 0 gpio PHI [26] ; Wait for clock to go low
out pins, 3 ; Set control pins (19-21)
wait 1 gpio PHI [24] ; Wait for clock to go high
jmp pin read ; Jump to read if IN pin is high
jmp done ; Jump to done if write and wait
read:
in pins, 8 ; Read data bus into isr
push block ; Push isr to fifo
in pins, 8 ; Read data bus into isr
push block ; Push isr to fifo
done:
out pins, 3 ; Set control to next 3 bits from fifo
wait 0 gpio PHI ; Wait for clock to go low
out pins, 3 ; Set control to next 3 bits from fifo
wait 0 gpio PHI ; Wait for clock to go low
.wrap

; Data and address bus program
.program data_bus
.wrap_target
pull block ; Pull data from FIFO
wait 1 irq DATAIRQ ; Wait for data irq signal
; wait 1 gpio PHI ; Wait for clock to go high ; ISSUE: For async this is shit, for sync this is great
wait 1 irq DATAIRQ ; Wait for data irq signal ~ should trigger exactly 1 cycle after datairq
wait 0 gpio PHI [26] ; Wait for clock to go low
out pins, 16 ; Set data bus pins
out pindirs 16 ; Set pin directions
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14 changes: 7 additions & 7 deletions src/tusb_config.h
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Original file line number Diff line number Diff line change
Expand Up @@ -111,20 +111,20 @@
#define CFG_TUD_VENDOR 1

// CDC Endpoint transfer buffer size, more is faster
#define CFG_TUD_CDC_EP_BUFSIZE (TUD_OPT_HIGH_SPEED ? 512 : 64)
#define CFG_TUD_CDC_EP_BUFSIZE (TUD_OPT_HIGH_SPEED ? 512 : 64) // Even at 512KB only 64KB will be used

// CDC FIFO size of TX and RX
#define CFG_TUD_CDC_RX_BUFSIZE (TUD_OPT_HIGH_SPEED ? 512 : 64)
#define CFG_TUD_CDC_TX_BUFSIZE (TUD_OPT_HIGH_SPEED ? 512 : 64)
#define CFG_TUD_CDC_RX_BUFSIZE (TUD_OPT_HIGH_SPEED ? 512 : 64) // Even at 512KB only 64KB will be used
#define CFG_TUD_CDC_TX_BUFSIZE (TUD_OPT_HIGH_SPEED ? 512 : 64) // Even at 512KB only 64KB will be used

// MIDI FIFO size of TX and RX
#define CFG_TUD_MIDI_RX_BUFSIZE (TUD_OPT_HIGH_SPEED ? 512 : 64)
#define CFG_TUD_MIDI_TX_BUFSIZE (TUD_OPT_HIGH_SPEED ? 512 : 64)
#define CFG_TUD_MIDI_RX_BUFSIZE (TUD_OPT_HIGH_SPEED ? 512 : 64) // Even at 512KB only 64KB will be used
#define CFG_TUD_MIDI_TX_BUFSIZE (TUD_OPT_HIGH_SPEED ? 512 : 64) // Even at 512KB only 64KB will be used

// Vendor FIFO size of TX and RX
// If not configured vendor endpoints will not be buffered
#define CFG_TUD_VENDOR_RX_BUFSIZE (TUD_OPT_HIGH_SPEED ? 512 : 64)
#define CFG_TUD_VENDOR_TX_BUFSIZE (TUD_OPT_HIGH_SPEED ? 512 : 64)
#define CFG_TUD_VENDOR_RX_BUFSIZE (TUD_OPT_HIGH_SPEED ? 512 : 64) // Even at 512KB only 64KB will be used
#define CFG_TUD_VENDOR_TX_BUFSIZE (TUD_OPT_HIGH_SPEED ? 512 : 64) // Even at 512KB only 64KB will be used


#ifdef __cplusplus
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