bug fix for converter

LeonMac · Apr 18, 2019 · c7f3136 · c7f3136
1 parent 05bb433
commit c7f3136
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Showing 2 changed files with 4 additions and 3 deletions.
diff --git a/bittware_xupvvh/src/rtl/bittware_xupvvh_top.sv b/bittware_xupvvh/src/rtl/bittware_xupvvh_top.sv
@@ -31,8 +31,8 @@ always_ff @ (posedge clk_100) rst_100_r <= {rst_100_r, ~sys_reset_n};
 always_ff @ (posedge clk_200) rst_200_r <= {rst_200_r, ~sys_reset_n};
 always_ff @ (posedge clk_300) rst_300_r <= {rst_300_r, ~sys_reset_n};
 
-if_axi_stream #(.DAT_BYTS(1)) uart_axi_rx(clk_300);
-if_axi_stream #(.DAT_BYTS(1)) uart_axi_tx(clk_300);
+if_axi_stream #(.DAT_BYTS(8)) uart_axi_rx(clk_300);
+if_axi_stream #(.DAT_BYTS(8)) uart_axi_tx(clk_300);
 
 always_comb begin
   led_pins[3:0] = 0;

diff --git a/bittware_xupvvh/src/rtl/uart_wrapper.sv b/bittware_xupvvh/src/rtl/uart_wrapper.sv
@@ -34,7 +34,8 @@ enum {UART_STARTUP, UART_LOOPBACK, UART_TX_STREAM, UART_RX_STREAM, UART_WAIT_STR
 
 // Interfaces before data width conversion
 if_axi_stream #(.DAT_BYTS(1), .CTL_BYTS(1)) tx_int_if (i_clk);
-if_axi_stream #(.DAT_BYTS(8), .CTL_BYTS(1)) rx_int_if (i_clk);
+if_axi_stream #(.DAT_BYTS(1), .CTL_BYTS(1)) rx_int_if (i_clk);
+
 
 logic interrupt;
 logic [31:0] uart_axi_wdata, uart_axi_rdata;