Add support for SVE types and registers in inline assembly #1
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The representation of the element type has been changed to be a slice rather than a zero length array. Two feature gates are now required in core_arch unsized fn params and unsized locals. This still leaves unsized return types being an issue. For this we are currently bypassing some of the `Sized` trait checking to pass when the type is scalable simd. This still leaves the copy issue. For that we have marked scalable simd types as trivally pure clone copy. We have still had to remove some trait checks for the copy trait with this though as they are still performed in certain situations. The implementation of `transmute` is also an issue for us. For this a new SIMD intrinsic has been created simd_reinterpret which performs a transmute on SIMD vectors. A few intrinsics need to be able to produce an LLVM `undef` this intrinsic will also produce that when given a zero sized input.
This patch passes three new register constraints (y, Upa, Upl) to LLVM, along with allowing the SVE types to be passed in and out of inline assembly.
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This patch passes three new register constraints (y, Upa, Upl) to LLVM, along with allowing the SVE types to be passed in and out of inline assembly.