Updating README and pdf files for v1.4

README.md

@@ -1,5 +1,5 @@
 The work in this repo is the result of a Zcash foundation grant to develop open-source FPGA code that can be used to accelerate various aspects of the network.
-**An Architecture document is [here](zcash_fpga_design_doc_v1.3.pdf)**.
+**An Architecture document is [here](zcash_fpga_design_doc_v1.4.pdf)**.
 
 While mainly developed for Equihash verification and elliptic curve operations on the secp256k1 and bls12-381 curves, the code (ip_cores) used in this repo can also be applied to other curves by
 changing parameters / minimum modification to equations.
@@ -44,9 +44,9 @@ These contain shared IP cores that are used by the projects in this repo. These
 * Barret reduction for modulo reduction when the modulus does not allow fast reduction
   - Both a fully pipelined high performance version and a slower but smaller resource utilization version
 * Fully parallel multiplier with carry save adder tree and RAM for modular reduction
-  - Fully pipelined, 3x performance over Karatsuba + Barret, but uses FPGA RAM  
+  - Fully pipelined, 3x performance over Karatsuba + Barret, but uses FPGA RAM
 * Multiplier using carry tree to accumulate products with BRAM for modular reduction
-  - 3x performance over Karatsuba + Barret approach
+  - 3x performance over Karatsuba + Barret approach, but takes more LUTs / RAM
 * Addition and subtraction modules
   - Fully parameterized so that they can be used for large bit-width arithmetic
 * Extended Euclidean algorithm for calculating multiplicative inverses

ip_cores/accum_mult_mod/scripts/generate_files.py

@@ -34,10 +34,6 @@
 URAM_PERCENT = 50
 USE_INIT = 1
 
-#8b3f481e3aaa0f1a09e30ed741d8ae4fcf5e095d5d00af600db18cb2c04b3edd03cc744a2888ae40caa232946c5e7e1  ^2 =
-#64a3a594868a2a4dab071ff6d880ae0f459c87e11ab01b3454b95a7d6a93f853f6e07f754b6e7933799e0afe2779a56
-
-
 RES_W = A_DSP_W+B_DSP_W
 NUM_COL = (BITS+A_DSP_W-1)//A_DSP_W;
 NUM_ROW = (BITS+B_DSP_W-1)//B_DSP_W;