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Updated to add ADD and SUB functions, memory map fixes, and test bench
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updates
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bsdevlin authored and bsdevlin committed Jun 30, 2019
1 parent ac887e3 commit cb18f74
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Showing 5 changed files with 234 additions and 33 deletions.
53 changes: 53 additions & 0 deletions aws/cl_zcash/verif/tests/test_zcash.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -234,9 +234,13 @@ endtask;
task test_bls12_381();
// Try writing and reading a slot
logic [1024*8-1:0] dat = 0;
logic failed = 0;
logic [31:0] rdata;
bls12_381_pkg::data_t slot_data;
bls12_381_pkg::inst_t inst;
bls12_381_interrupt_rpl_t interrupt_rpl;
fp2_jb_point_t out_p, exp_p;
logic [380:0] in_k = 381'h33333333333333333333333333333333333333333333333333333333333333333333333333333333333333333333333

// Make sure we aren't in reset
while(!tb.card.fpga.CL.zcash_fpga_top.bls12_381_top.inst_uram_reset.reset_done ||
Expand Down Expand Up @@ -274,6 +278,55 @@ task test_bls12_381();
$display("INFO: Wrote: 0x%x", inst);
assert(dat[2*8-1:0] == inst) else $fatal(1, "ERROR: Writing to slot and reading gave wrong results!");

slot_data = '{dat:in_k, pt:SCALAR};
for(int i = 0; i < 48; i = i + 4)
write_ocl_reg(.addr(`ZCASH_OFFSET + bls12_381_pkg::DATA_AXIL_START + 3*64 + i), .data(slot_data[i*8 +: 32]));


inst = '{code:SEND_INTERRUPT, a:16'd0, b:16'habcd, c:16'd0};
for(int i = 0; i < 8; i = i + 4)
write_ocl_reg(.addr(`ZCASH_OFFSET + bls12_381_pkg::INST_AXIL_START + 1*8 + i), .data(inst[i*8 +: 32]));


// Write to current slot to start
inst = '{code:FP2_FPOINT_MULT, a:16'd3, b:16'd0, c:16'd0};
for(int i = 0; i < 8; i = i + 4)
write_ocl_reg(.addr(`ZCASH_OFFSET + bls12_381_pkg::INST_AXIL_START + 0*8 + i), .data(inst[i*8 +: 32]));

fork
begin
while(stream_len == 0) read_stream(.data(stream_data), .len(stream_len));
interrupt_rpl = stream_data;

assert(interrupt_rpl.hdr.cmd == BLS12_381_INTERRUPT_RPL) else $fatal(1, "ERROR: Received non-interrupt message");
assert(interrupt_rpl.index == 16'habcd) else $fatal(1, "ERROR: Received wrong index value in message");
assert(interrupt_rpl.data_type == FP2_JB) else $fatal(1, "ERROR: Received wrong data type value in message");

stream_data = stream_data >> $bits(bls12_381_interrupt_rpl_t);

for (int i = 0; i < 6; i++)
out_p[i*381 +: 381] = stream_data[i*(48*8) +: 381];

if (out_p == exp_p) begin
$display("INFO: Output point matched expected:");
print_fp2_jb_point(out_p);
end else begin
$display("ERROR: Output point did NOT match expected:");
print_fp2_jb_point(out_p);
$display("Expected:");
print_fp2_jb_point(exp_p);
failed = 1;
end
end
begin
repeat(10000) @(posedge tb.card.fpga.clk_main_a0);
$fatal(1, "ERROR: No reply received from test_bls12_381");
end
join_any
disable fork;

if(failed) $fatal(1, "ERROR: Test FAILED test_bls12_381");

$display("test_bls12_381 PASSED");
endtask;

Expand Down
4 changes: 2 additions & 2 deletions zcash_fpga/src/rtl/bls12_381/bls12_381_axi_bridge.sv
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Expand Up @@ -95,11 +95,11 @@ always_ff @ (posedge i_clk) begin

// Read requests
if (inst_ram_read[READ_CYCLE]) begin
axi_lite_if.rdata <= inst_ram_if.q;
axi_lite_if.rdata <= inst_ram_if.q >> ((axi_lite_if.araddr - INST_AXIL_START) % INST_RAM_ALIGN_BYTE)*8;
axi_lite_if.rvalid <= 1;
end
if (data_ram_read[READ_CYCLE]) begin
axi_lite_if.rdata <= data_ram_if.q;
axi_lite_if.rdata <= data_ram_if.q >> ((axi_lite_if.araddr - DATA_AXIL_START) % DATA_RAM_ALIGN_BYTE)*8;
axi_lite_if.rvalid <= 1;
end

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2 changes: 2 additions & 0 deletions zcash_fpga/src/rtl/bls12_381/bls12_381_pkg.sv
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Expand Up @@ -90,6 +90,8 @@ package bls12_381_pkg;
COPY_REG = 8'h1,
SEND_INTERRUPT = 8'h6,

SUB_ELEMENT = 8'h10,
ADD_ELEMENT = 8'h11,
MUL_ELEMENT = 8'h12,
INV_ELEMENT = 8'h13,

Expand Down
140 changes: 140 additions & 0 deletions zcash_fpga/src/rtl/bls12_381/bls12_381_top.sv
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Expand Up @@ -185,6 +185,14 @@ always_ff @ (posedge i_clk) begin
if (cnt == 0) last_inst_cnt <= 0;
task_mul_element();
end
SUB_ELEMENT: begin
if (cnt == 0) last_inst_cnt <= 0;
task_sub_element();
end
ADD_ELEMENT: begin
if (cnt == 0) last_inst_cnt <= 0;
task_add_element();
end
SEND_INTERRUPT: begin
last_inst_cnt <= last_inst_cnt;
task_send_interrupt();
Expand Down Expand Up @@ -428,6 +436,138 @@ task get_next_inst();
end
endtask

task task_sub_element();
case(cnt)
0: begin
sub_out_if[2].rdy <= 1;
data_ram_sys_if.a <= curr_inst.a;
data_ram_read[0] <= 1;
cnt <= 1;
end
1: begin
if (data_ram_read[READ_CYCLE]) begin
sub_in_if[2].dat[0 +: $bits(fe_t)] <= curr_data.dat;
pt_l <= curr_data.pt;
data_ram_sys_if.a <= curr_inst.b;
data_ram_read[0] <= 1;
cnt <= 2;
end
end
2: begin
if (data_ram_read[READ_CYCLE]) begin
sub_in_if[2].dat[$bits(fe_t) +: $bits(fe_t)] <= curr_data.dat;
sub_in_if[2].val <= 1;
end
if (sub_out_if[2].val && sub_out_if[2].rdy) begin
data_ram_sys_if.a <= curr_inst.c;
new_data.dat <= sub_out_if[2].dat;
new_data.pt <= pt_l;
data_ram_sys_if.we <= 1;
cnt <= 5;
if (pt_l == FE2) begin
// FE2 requires extra logic
cnt <= 3;
end
end
end
3: begin
if (!(|data_ram_read)) begin
data_ram_sys_if.a <= curr_inst.a + 1;
data_ram_read[0] <= 1;
end
if (data_ram_read[READ_CYCLE]) begin
sub_in_if[2].dat[0 +: $bits(fe_t)] <= curr_data.dat;
pt_l <= curr_data.pt;
data_ram_sys_if.a <= curr_inst.b + 1;
data_ram_read[0] <= 1;
cnt <= 4;
end
end
4: begin
if (data_ram_read[READ_CYCLE]) begin
sub_in_if[2].dat[$bits(fe_t) +: $bits(fe_t)] <= curr_data.dat;
sub_in_if[2].val <= 1;
end
if (sub_out_if[2].val && sub_out_if[2].rdy) begin
data_ram_sys_if.a <= curr_inst.c + 1;
new_data.dat <= sub_out_if[2].dat;
new_data.pt <= pt_l;
data_ram_sys_if.we <= 1;
cnt <= 5;
end
end
5: begin
get_next_inst();
end
endcase
endtask;

task task_add_element();
case(cnt)
0: begin
add_out_if[2].rdy <= 1;
data_ram_sys_if.a <= curr_inst.a;
data_ram_read[0] <= 1;
cnt <= cnt + 1;
end
1: begin
if (data_ram_read[READ_CYCLE]) begin
add_in_if[2].dat[0 +: $bits(fe_t)] <= curr_data.dat;
pt_l <= curr_data.pt;
data_ram_sys_if.a <= curr_inst.b;
data_ram_read[0] <= 1;
cnt <= 2;
end
end
2: begin
if (data_ram_read[READ_CYCLE]) begin
add_in_if[2].dat[$bits(fe_t) +: $bits(fe_t)] <= curr_data.dat;
add_in_if[2].val <= 1;
end
if (add_out_if[2].val && add_out_if[2].rdy) begin
data_ram_sys_if.a <= curr_inst.c;
new_data.dat <= add_out_if[2].dat;
new_data.pt <= pt_l;
data_ram_sys_if.we <= 1;
cnt <= 5;
if (pt_l == FE2) begin
// FE2 requires extra logic
cnt <= 3;
end
end
end
3: begin
if (!(|data_ram_read)) begin
data_ram_sys_if.a <= curr_inst.a + 1;
data_ram_read[0] <= 1;
end
if (data_ram_read[READ_CYCLE]) begin
add_in_if[2].dat[0 +: $bits(fe_t)] <= curr_data.dat;
pt_l <= curr_data.pt;
data_ram_sys_if.a <= curr_inst.b + 1;
data_ram_read[0] <= 1;
cnt <= 4;
end
end
4: begin
if (data_ram_read[READ_CYCLE]) begin
add_in_if[2].dat[$bits(fe_t) +: $bits(fe_t)] <= curr_data.dat;
add_in_if[2].val <= 1;
end
if (add_out_if[2].val && add_out_if[2].rdy) begin
data_ram_sys_if.a <= curr_inst.c + 1;
new_data.dat <= add_out_if[2].dat;
new_data.pt <= pt_l;
data_ram_sys_if.we <= 1;
cnt <= 5;
end
end
5: begin
get_next_inst();
end
endcase
endtask;

task task_mul_element();
case(cnt)
0: begin
Expand Down
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