add Xilinx FIFO and fix flow control

HowToLoveChina · Sep 10, 2020 · b1bdc38 · b1bdc38
1 parent 4927d41
commit b1bdc38
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Showing 7 changed files with 1,322 additions and 664 deletions.
diff --git a/aws/cl_zcash/build/scripts/synth_cl_zcash.tcl b/aws/cl_zcash/build/scripts/synth_cl_zcash.tcl
@@ -75,6 +75,8 @@ read_ip [ list \
 
 puts "AWS FPGA: Generating IP blocks";
 
+upgrade_ip [get_ips *]
+
 set_property generate_synth_checkpoint false [get_files axis_dwidth_converter_64_to_8.xci]
 set_property generate_synth_checkpoint false [get_files axis_dwidth_converter_8_to_64.xci]
 set_property generate_synth_checkpoint false [get_files axis_dwidth_converter_4_to_8.xci]

diff --git a/aws/cl_zcash/ip/cl_sde_ip_setup.tcl b/aws/cl_zcash/ip/cl_sde_ip_setup.tcl
@@ -10,6 +10,7 @@ axis_dwidth_converter_48_to_8/axis_dwidth_converter_48_to_8.xci
 axis_dwidth_converter_4_to_8/axis_dwidth_converter_4_to_8.xci
 axis_dwidth_converter_8_to_4/axis_dwidth_converter_8_to_4.xci
 ila_2/ila_2.xci
+fifo_generator_0/fifo_generator_0.xci
 }
 
 upgrade_ip [get_ips *]
@@ -21,4 +22,5 @@ generate_target all [get_files  axis_dwidth_converter_8_to_64/axis_dwidth_conver
 generate_target all [get_files axis_dwidth_converter_48_to_8/axis_dwidth_converter_48_to_8.xci]
 generate_target all [get_files  axis_dwidth_converter_4_to_8/axis_dwidth_converter_4_to_8.xci]
 generate_target all [get_files  axis_dwidth_converter_8_to_4/axis_dwidth_converter_8_to_4.xci]
-generate_target all [get_files  ila_2/ila_2.xci]
+generate_target all [get_files  ila_2/ila_2.xci]
+generate_target all [get_files  fifo_generator_0/fifo_generator_0.xci]
diff --git a/aws/cl_zcash/ip/fifo_generator_0.xci b/aws/cl_zcash/ip/fifo_generator_0.xci
diff --git a/aws/cl_zcash/ip/mk_clean b/aws/cl_zcash/ip/mk_clean
@@ -6,4 +6,5 @@ rm -rf axis_dwidth_converter_48_to_8/
 rm -rf axi_fifo_mm_s_lite/
 rm -rf axis_dwidth_converter_4_to_8/
 rm -rf axis_dwidth_converter_8_to_4/
-rm -rf ila_2/
+rm -rf ila_2/
+rm -rf fifo_generator_0.xci/
diff --git a/aws/cl_zcash/ip/run_cl_sde_ip_flow b/aws/cl_zcash/ip/run_cl_sde_ip_flow
@@ -6,6 +6,7 @@ mkdir axis_dwidth_converter_48_to_8
 mkdir axis_dwidth_converter_4_to_8
 mkdir axis_dwidth_converter_8_to_4
 mkdir ila_2
+mkdir fifo_generator_0
 
 cp axi_fifo_mm_s_0.xci axi_fifo_mm_s_0/axi_fifo_mm_s_0.xci
 cp axi_fifo_mm_s_lite.xci axi_fifo_mm_s_lite/axi_fifo_mm_s_lite.xci
@@ -15,6 +16,7 @@ cp axis_dwidth_converter_48_to_8.xci axis_dwidth_converter_48_to_8/axis_dwidth_c
 cp axis_dwidth_converter_4_to_8.xci axis_dwidth_converter_4_to_8/axis_dwidth_converter_4_to_8.xci
 cp axis_dwidth_converter_8_to_4.xci axis_dwidth_converter_8_to_4/axis_dwidth_converter_8_to_4.xci
 cp ila_2.xci ila_2/ila_2.xci
+cp fifo_generator_0.xci fifo_generator_0/fifo_generator_0.xci
 
 vivado -mode batch -source cl_sde_ip_setup.tcl