add CDNA3 flash attention forward kernels#33
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…causal) FlashAttention-2 forward pass using mfma_f32_16x16x16 with online softmax (base-2 exp), GQA head mapping, and register-buffer pipeline for overlapping global loads with MFMA compute. Beats PyTorch SDPA by 1.25-1.37x on MI300X. Closes HazyResearch#12 Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
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Hi! Thank you for the contribution. I compiled the gqa and gqa causal kernels and found vgpr spillage and scratch usage. I think the performance would improve a lot once we get rid of those! |
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Root cause: gfx950 hardware race in v_mfma_f32_16x16x128_f8f6f4's source- operand pipeline. When buffer_load_lds_dwordx4 writes to the same LDS slot from which an in-flight mfma's source VGPR (b0) was just ds_read-loaded, the mfma's internal source-forwarding latches refresh from that LDS slot mid-execution and pull in partially-written bytes, corrupting mfma output. Decisive evidence (bisection HazyResearch#33): moving the G::load(Bs[tic], k+2) from between the two rrr_mma(...,b0) calls to AFTER both mmas eliminated the race at K=384 (5/5 bit-equal). At K=1536 this introduced a separate iter-to-iter data dependency bug because Bs[tic] is the ping-pong slot expected to be written for k+2. Fix: Bs[2] -> Bs[3] with 3-way rotation (b_cur, b_nxt, b_wrt). Each iter writes to b_wrt which is always distinct from b_cur (source of in-flight mfma's b0). After rotation: b_cur <- b_nxt, b_nxt <- b_wrt, b_wrt <- b_cur. Epilog 1 reads Bs[b_cur], epilog 2 reads Bs[b_nxt]. Verified: 378/378 shapes 3-run bit-equal across K in {256..2048}, N in {128..4096}, B in {1,4,16}, M_g in {256,1024,4096}. Plus baseline worst-case (qwen-down K=1536 B=16 M_g=8192) 5/5 bit-equal. Why all prior sync attempts failed: - vmcnt/lgkmcnt drain external memory completion, NOT mfma's internal source-forwarding pipeline - s_barrier syncs warps, no effect on intra-warp HW pipeline - s_nop 256cyc adds cycle delay, doesn't prevent LDS-write contamination of mfma's source-LDS pointer (structural, not timing) - sched_barrier(0) forbids compiler reorder; offending order is intentional Why B triggers but A doesn't: A is loaded via rcr_8w_load_hoist (direct vmem->VGPR, no LDS slot for HW to refresh from). B goes vmem->LDS->VGPR; mfma's source-forwarding can refresh from B's source LDS slot during exec. Why dense doesn't trigger: dense K-loop doesn't issue vmem->LDS to source- slot mid-mfma. Same v_mfma_f32_16x16x128_f8f6f4 opcode, no trigger. Co-Authored-By: Claude Opus 4.7 <noreply@anthropic.com>
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Summary
Performance (MI300X, B=4 H=32 H_KV=8 N=1024)
Test plan
Closes #12
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