more galileo stuff

include/clock.h

@@ -7,6 +7,18 @@ extern	int32	slnonempty;	/* nonzero if sleepq is nonempty	*/
 extern	int32	*sltop;		/* ptr to key in first item on sleepq	*/
 extern	uint32	preempt;	/* preemption counter			*/
 
+#ifdef X86_GALILEO
+/* Intel 8254-2 clock chip constants */
+
+#define CLOCKBASE       0x40            /* I/O base port of clock chip  */
+#define CLOCK0          CLOCKBASE
+#define CLKCNTL         (CLOCKBASE+3)   /* chip CSW I/O port            */
+
+
+#define CLKTICKS_PER_SEC  1000  /* clock timer resolution               */
+
+#endif /* X86_GALILEO */
+
 #ifdef ARM_QEMU
 #define CLKTICKS_PER_SEC  1000
 

include/delay.h

@@ -3,6 +3,15 @@
 /*
  * Delay units are in microseconds.
  */
+#ifdef X86_GALILEO
+#define	DELAY(n)                                	\
+{                                               	\
+	register int i = 0;				\
+							\
+	while(i < (n * 100)) i++;			\
+}			
+
+#else /* !X86_GALILEO */
 #define	DELAY(n)                                	\
 {                                               	\
 	volatile long N = 2*n;				\
@@ -11,6 +20,7 @@
 		N--;					\
 	}						\
 }
+#endif
 
 /*
  * Delay units are in milli-seconds.
@@ -23,3 +33,4 @@
 		DELAY(1000);				\
 	}						\
 }
+

include/platform/x86-galileo/icu.h

@@ -0,0 +1,9 @@
+/* icu.h */
+
+#define	ICU1	0x20		/* I/O port address, 8259A #1		*/
+#define	ICU2	0xA0		/* I/O port address, 8258A #2		*/
+
+#define	OCR	ICU1		/* Operation Command Register		*/
+#define	IMR	(ICU1+1)	/* Interrupt Mask Register		*/
+
+#define	EOI	0x20		/* non-specific end of interrupt	*/

include/platform/x86-galileo/icu.s

@@ -0,0 +1,15 @@
+/* icu.s */
+
+/* Interrupt controller symbolic constants for assembly language	*/
+/*	Note: icu.h defines equivalent constants for C functions	*/
+
+	.set	ICU1,0x20	/* I/O port address, 8259A #1		*/
+	.set	ICU2,0xA0	/* I/O port address, 8258A #2		*/
+
+	.set	OCW1_2,ICU1	
+	.set	OCW2_2,ICU2
+
+	.set	IMR1,ICU1 + 1	/* Interrupt Mask Register for #1	*/
+	.set	IMR2,ICU2 + 1	/* Interrupt Mask Register for #2	*/
+
+	.set	EOI,0x20	/* non-specific end of interrupt	*/

include/platform/x86-galileo/multiboot.h

@@ -0,0 +1,59 @@
+/* multiboot.h - definitions for the multiboot header */
+
+struct mbootinfo {
+	uint32	flags;			/* Multiboot information flags	*/
+	uint32	mem_lower;		/* Memory in KB below 1M	*/
+	uint32	mem_upper;		/* Memory in KB above 1M	*/
+	uint32	boot_device;		/* Boot device containing image	*/
+	uint32	cmdline;		/* Address of command line	*/
+	uint32	mods_count;		/* No. of modules loaded	*/
+	uint32	mods_addr;		/* Address to the module info	*/
+	uint32	syms[4];		/* Info regarding ELF sections	*/
+	uint32	mmap_length;		/* Length(bytes) of mmap region	*/
+	uint32	mmap_addr;		/* Address of the mmap regios	*/
+	uint32	drives_length;		/* Size of drives structures	*/
+	uint32	drives_addr;		/* Address of Drive structures	*/
+	uint32	config_table;		/* Address of ROM config table	*/
+	uint32	boot_loader_name;	/* Address of boot loader name	*/
+	uint32	apm_table;		/* Address of APM table		*/
+	uint32	vbe_control_info;	/* VBE control info		*/
+	uint32	vbe_mode_info;		/* VBE mode info		*/
+	uint16	vbe_mode;		/* Current Video mode		*/
+	uint16	vbe_interface_seg;	/* VBE related information	*/
+	uint16	vbe_interface_off;	/* VBE related information	*/
+	uint32	vbe_interface_len;	/* VBE related informarion	*/
+};
+
+struct mbmregion {
+	uint32	size;			/* Entry Size			*/
+	uint64	base_addr;		/* Memory region base address	*/
+	uint64	length;			/* Memory region length		*/
+	uint32	type;			/* Memory region type		*/
+};
+
+/* Multiboot header magic number	*/
+#define	MULTIBOOT_HEADER_MAGIC  	0x1BADB002
+
+/* Flags for required multiboot info	*/
+#define	MULTIBOOT_HEADER_FLAGS  	0x00010003
+
+/* Multiboot signature verification	*/
+#define MULTIBOOT_SIGNATURE		0x2BADB002
+
+/* mem_upper mem_lower fields valid	*/
+#define MULTIBOOT_BOOFINFO_MEM		0x00000001
+
+/* boot device field valid		*/
+#define MULTIBOOT_BOOTINFO_BOOTDEV	0x00000002
+
+/* cmdline field valid			*/
+#define MULTIBOOT_BOOTINFO_CMDLINE	0x00000004
+
+/* mods_count mods_addr valid		*/
+#define MULTIBOOT_BOOTINFO_MODS		0x00000008
+
+/* mmap_length mmap_addr valid		*/
+#define MULTIBOOT_BOOTINFO_MMAP		0x00000040
+
+/* Usable memory region 		*/
+#define	MULTIBOOT_MMAP_TYPE_USABLE	0x00000001

include/platform/x86-galileo/pci.h

@@ -0,0 +1,80 @@
+/*
+ * pci.h
+ */
+
+
+#define PCI_MAX_BUSES				256
+#define PCI_DEVICES_PER_BUS			32
+#define PCI_FUNCTIONS_PER_DEVICE	8
+#define PCI_BUS_MASK				(PCI_MAX_BUSES - 1)
+#define PCI_DEV_MASK				(PCI_DEVICES_PER_BUS - 1)
+#define PCI_FUNC_MASK				(PCI_FUNCTIONS_PER_DEVICE - 1)
+#define PCIE_BYTES_PER_FUNCTION		0x1000
+#define PCIE_BYTES_PER_DEVICE		(PCIE_BYTES_PER_FUNCTION *			\
+									  PCI_FUNCTIONS_PER_DEVICE)
+#define PCIE_BYTES_PER_BUS			(PCIE_BYTES_PER_DEVICE *			\
+									  PCI_DEVICES_PER_BUS)
+
+#define PCI_BARS_PER_HEADER			6	   		/* Base addr regs per header */
+
+#define PCI_HEADER_TYPE0_SIZE		0x40		/* Size of type0 header */
+#define	PCI_HDR_TYPE_MULTIFUNCTION	(1 << 7)	/* Multifunction device */
+
+#define PCI_BUS_SHIFT			16				/* Bits to shift bus value */
+#define PCI_DEV_SHIFT			3				/* Bits to shift dev value */
+
+/* Definitions of PCI base address register (bar) bits:*/
+#define PCI_BAR_REGION_TYPE_IO_MASK	1			/* 0=memory space, 1=I/O */
+#define PCI_BAR_LOCATABLE_1MB_MASK	2			/* 1=Must be < 1MB */
+#define PCI_BAR_LOCATABLE_64B_MASK	4			/* 1=Any 64-bit phys addr */
+#define PCI_BAR_LOCATABLE_PREFETCH	8			/* 1=Prefetchable */
+#define PCI_BAR_BASE_ADDRESS_MASK	0xfffffff0	/* MMIO base phys addr mask */
+
+#ifndef offsetof
+#define offsetof(type, member) ((int)((unsigned int)&((type *)0)->member))
+#endif
+
+/* Define the layout of PCI config headers (type 0) */
+
+struct __attribute__ ((__packed__)) pci_config_header {
+	/*	      PCI header field			Byte offset */
+	unsigned short	vendorID;					/* 0x0 */
+	unsigned short	deviceID;					/*   2 */
+	unsigned short	command;					/*   4 */
+	unsigned short	status;						/*   6 */
+	unsigned char	revID;						/*   8 */
+	unsigned char	progIF;						/*   9 */
+	unsigned char	subClass;					/*   a */
+	unsigned char	classCode;					/*   b */
+	unsigned char	clSize;						/*   c */
+	unsigned char	latencyTimer;				/*   d */
+	unsigned char	headerType;					/*   e */
+	unsigned char	BIST;						/*   f */
+	unsigned int	bars[PCI_BARS_PER_HEADER];	/*   10 */
+	unsigned int	cardbusCISPtr;				/*   28 */
+	unsigned short	subsystemVendorID;			/*   2c */
+	unsigned short	subsystemID;				/*   2e */
+	unsigned int	expansionROMAddr;			/*   30 */
+	unsigned char	capabilitiesPtr;			/*   34 */
+	unsigned char	reserved0;					/*   35 */
+	unsigned char	reserved1;					/*   36 */
+	unsigned char	reserved2;					/*   37 */
+	unsigned int	reserved3;					/*   38 */
+	unsigned char	interruptLine;				/*   3c */
+	unsigned char	interruptPin;				/*   3d */
+	unsigned char	minGrant;					/*   3e */
+	unsigned char	maxLatency;					/*   3f */
+};
+
+extern int pci_init(void);
+extern int find_pci_device(int32, int32, int32);
+extern struct eth_pd*	eth_txring;
+extern struct eth_pd*	eth_rxring;
+
+extern int pci_read_config_byte(uint32, int, unsigned char *);
+extern int pci_read_config_word(uint32, int, uint16 *);
+extern int pci_read_config_dword(uint32, int, uint32 *);
+extern int pci_write_config_byte(uint32, int, unsigned char);
+extern int pci_write_config_word(uint32, int, uint16);
+extern int pci_write_config_dword(uint32, int, uint32);
+extern int pci_get_dev_mmio_base_addr(uint32, int, void **);

include/platform/x86-galileo/pxe.h

@@ -0,0 +1,43 @@
+/* pxe.h - Definitions for Pre-Execution Boot Environment */
+
+/* BIOS SYSID Structure Table */
+#define SYSID_ENTRY_POINT_SADDR 0x000E0000
+#define SYSID_ENTRY_POINT_EADDR 0x000FFFFF
+
+#define SYSID_ENTRY_POINT_HDR   "_SYSID_"
+#define SYSID_ENTRY_UUID_HDR    "_UUID_"
+
+#pragma pack(1)
+struct sysid_bios_struct
+{
+	byte header[6];
+	byte checksum;
+	uint16 len;
+};
+#pragma pack()
+
+#pragma pack(1)
+struct sysid_entry_point
+{
+	byte   header[7];
+	byte   checksum;
+	uint16 len;
+	uint32 bios_structure_addr;
+	uint16 bios_struct_count;
+	byte   sysid_bios_revision;
+};
+#pragma pack()
+
+struct sysid_entry_point* get_sysid_entry_point();
+char* get_uuid(uint16* uuid_len);
+
+/* PXE client specification string                               */
+/*   Tells the boot server information about client architecture */
+/*   and supported PXE version                                   */
+/*   Client architecture - 000000 - IA x86 PC                    */
+/*   PXE Version - 2.1                                           */
+#define PXE_CLIENT_STRING      "PXEClient:Arch:00000:UNDI:002001"
+#define PXE_CLIENT_STRING_LEN  32
+
+int32 build_dhcp_discover_pxe(struct dhcpmsg* dmsg);
+int32 build_dhcp_request_pxe(struct dhcpmsg* dmsg, const struct dhcpmsg* dmsg_offer);