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Description

The goal of this PR is to add the GCC/ARMClang non-MPU port variant for ARM Cortex-R82 processor ( ARMv8-R AArch64 based ).

This port has the following features:

  • Uses single security state (non TrustZone).
  • Supports SMP (Symmetric multi-processing).
  • Doesn't support Hypervisor (EL2).
  • Doesn't support neither PMSA (MPU) nor VMSA (MMU).

Test Steps

Checklist:

  • I have tested my changes. No regression in existing tests.
  • I have modified and/or added unit-tests to cover the code changes in this Pull Request.

Related Issue

By submitting this pull request, I confirm that you can use, modify, copy, and redistribute this contribution, under the terms of your choice.

The goal of this commit is to add the GCC/ARMClang non-MPU
port variant for ARM Cortex-R82 processor which is
ARMv8-R AArch64 based.
The work done is inspired by the GCC ARM_AARCH64 FreeRTOS port.

This port has the following features:
* Uses single security state (non TrustZone).
* Supports SMP (Symmetric multi-processing).
* Doesn't support Hypervisor (EL2).
* Doesn't support neither PMSA (MPU) nor VMSA (MMU).

Signed-off-by: Ahmed Ismail <[email protected]>
@AhmedIsmail02 AhmedIsmail02 force-pushed the add-cortex-r82-non-mpu-gcc-armclang-port branch from d301109 to 255b9b6 Compare July 3, 2025 16:17
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sonarqubecloud bot commented Jul 9, 2025

@jasonpcarroll
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Hi @AhmedIsmail02,

Apologies for the late response. I will reach out to someone with a bit more familiarity with this architecture (and has a board to test) to take a look.

Best,

Jason Carroll

@AhmedIsmail02
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Hi @jasonpcarroll,

Thanks for getting back to me.

Sure, you can refer them to use the example available here which runs on Arm's FVP.

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sonarqubecloud bot commented Sep 1, 2025

uint64_t ullPortInterruptNestings[ configNUMBER_OF_CORES ] = { 0 };

/* Flag to control tick ISR handling, this is made true just before schedular start. */
__attribute__( ( section( ".shared_ram" ) ) )
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Why does it need to be placed in shared_ram section?

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4 participants