librelane/def/heichips25_template_small_cryo.def : moved and resized i_in and i_out ports#9
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…analog pins # Conflicts: # librelane/def/heichips25_template_small_cryo.def
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I moved and resized the analog ports in heichips25_template_small_cryo.def for better routing in the tile.
Please update if consistent with top level design rules.