Skip to content

FOSSEE Summer fellowship 2025 : Failed IC's by Athish #386

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Open
wants to merge 2 commits into
base: master
Choose a base branch
from
Open

FOSSEE Summer fellowship 2025 : Failed IC's by Athish #386

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
2 commits
Select commit Hold shift + click to select a range
5b8b5b8
Failed IC1 ICM7555
Athish04 Jul 13, 2025
a94a683
Failed IC2
Athish04 Jul 13, 2025
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
201 changes: 201 additions & 0 deletions library/SubcircuitLibrary/ICM7555/ICM7555-cache.lib
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -0,0 +1,201 @@
EESchema-LIBRARY Version 2.3
#encoding utf-8
#
# PORT
#
DEF PORT U 0 40 Y Y 26 F N
F0 "U" 50 100 30 H V C CNN
F1 "PORT" 0 0 30 H V C CNN
F2 "" 0 0 60 H V C CNN
F3 "" 0 0 60 H V C CNN
DRAW
A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
S -100 50 100 -50 0 1 0 N
X ~ 1 250 0 100 L 30 30 1 1 B
X ~ 2 250 0 100 L 30 30 2 1 B
X ~ 3 250 0 100 L 30 30 3 1 B
X ~ 4 250 0 100 L 30 30 4 1 B
X ~ 5 250 0 100 L 30 30 5 1 B
X ~ 6 250 0 100 L 30 30 6 1 B
X ~ 7 250 0 100 L 30 30 7 1 B
X ~ 8 250 0 100 L 30 30 8 1 B
X ~ 9 250 0 100 L 30 30 9 1 B
X ~ 10 250 0 100 L 30 30 10 1 B
X ~ 11 250 0 100 L 30 30 11 1 B
X ~ 12 250 0 100 L 30 30 12 1 B
X ~ 13 250 0 100 L 30 30 13 1 B
X ~ 14 250 0 100 L 30 30 14 1 B
X ~ 15 250 0 100 L 30 30 15 1 B
X ~ 16 250 0 100 L 30 30 16 1 B
X ~ 17 250 0 100 L 30 30 17 1 B
X ~ 18 250 0 100 L 30 30 18 1 B
X ~ 19 250 0 100 L 30 30 19 1 B
X ~ 20 250 0 100 L 30 30 20 1 B
X ~ 21 250 0 100 L 30 30 21 1 B
X ~ 22 250 0 100 L 30 30 22 1 B
X ~ 23 250 0 100 L 30 30 23 1 B
X ~ 24 250 0 100 L 30 30 24 1 B
X ~ 25 250 0 100 L 30 30 25 1 B
X ~ 26 250 0 100 L 30 30 26 1 B
ENDDRAW
ENDDEF
#
# adc_bridge_1
#
DEF adc_bridge_1 U 0 40 Y Y 1 F N
F0 "U" 0 0 60 H V C CNN
F1 "adc_bridge_1" 0 150 60 H V C CNN
F2 "" 0 0 60 H V C CNN
F3 "" 0 0 60 H V C CNN
DRAW
S -400 200 350 -50 0 1 0 N
X IN1 1 -600 50 200 R 50 50 1 1 I
X OUT1 2 550 50 200 L 50 50 1 1 O
ENDDRAW
ENDDEF
#
# d_inverter
#
DEF d_inverter U 0 40 Y Y 1 F N
F0 "U" 0 -100 60 H V C CNN
F1 "d_inverter" 0 150 60 H V C CNN
F2 "" 50 -50 60 H V C CNN
F3 "" 50 -50 60 H V C CNN
DRAW
P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N
X ~ 1 -300 0 200 R 50 50 1 1 I
X ~ 2 300 0 200 L 50 50 1 1 O I
ENDDRAW
ENDDEF
#
# d_nor
#
DEF d_nor U 0 40 Y Y 1 F N
F0 "U" 0 0 60 H V C CNN
F1 "d_nor" 50 100 60 H V C CNN
F2 "" 0 0 60 H V C CNN
F3 "" 0 0 60 H V C CNN
DRAW
A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
A -25 -124 325 574 323 0 1 0 N 150 150 250 50
A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
P 2 0 1 0 -250 -50 150 -50 N
P 2 0 1 0 -250 150 150 150 N
X IN1 1 -450 100 215 R 50 50 1 1 I
X IN2 2 -450 0 215 R 50 50 1 1 I
X OUT 3 450 50 200 L 50 50 1 1 O I
ENDDRAW
ENDDEF
#
# dac_bridge_1
#
DEF dac_bridge_1 U 0 40 Y Y 1 F N
F0 "U" 0 0 60 H V C CNN
F1 "dac_bridge_1" 0 150 60 H V C CNN
F2 "" 0 0 60 H V C CNN
F3 "" 0 0 60 H V C CNN
DRAW
S -400 200 350 -50 0 1 0 N
X IN1 1 -600 50 200 R 50 50 1 1 I
X OUT1 2 550 50 200 L 50 50 1 1 O
ENDDRAW
ENDDEF
#
# dc
#
DEF dc I 0 40 Y Y 1 F N
F0 "I" -200 100 60 H V C CNN
F1 "dc" -200 -50 60 H V C CNN
F2 "R1" -300 0 60 H V C CNN
F3 "" 0 0 60 H V C CNN
$FPLIST
1_pin
$ENDFPLIST
DRAW
C 0 0 150 0 1 0 N
P 2 0 1 0 0 -100 0 -100 N
P 2 0 1 0 0 100 -50 50 N
P 2 0 1 0 0 100 0 -100 N
P 2 0 1 0 0 100 50 50 N
X ~ 1 0 450 300 D 50 50 1 1 P
X ~ 2 0 -450 300 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# eSim_MOS_N
#
DEF eSim_MOS_N M 0 0 Y N 1 F N
F0 "M" 0 -150 50 H V R CNN
F1 "eSim_MOS_N" 100 -50 50 H V R CNN
F2 "" 300 -300 29 H V C CNN
F3 "" 100 -200 60 H V C CNN
ALIAS mosfet_n
DRAW
C 150 -200 111 0 1 10 N
P 2 0 1 10 130 -290 130 -250 N
P 2 0 1 0 130 -270 200 -270 N
P 2 0 1 10 130 -220 130 -180 N
P 2 0 1 0 130 -200 200 -200 N
P 2 0 1 10 130 -150 130 -110 N
P 2 0 1 0 130 -130 200 -130 N
P 2 0 1 0 200 -300 200 -270 N
P 2 0 1 0 200 -130 200 -100 N
P 3 0 1 10 110 -275 110 -125 110 -125 N
P 3 0 1 0 200 -200 300 -200 300 -250 N
P 4 0 1 0 140 -200 180 -215 180 -185 140 -200 F
X D 1 200 0 100 D 50 50 1 1 P
X G 2 -100 -200 210 R 50 50 1 1 P
X S 3 200 -400 100 U 50 50 1 1 P
X B 4 300 -350 98 U 47 47 1 1 P
ENDDRAW
ENDDEF
#
# eSim_MOS_P
#
DEF eSim_MOS_P M 0 0 Y N 1 F N
F0 "M" -50 50 50 H V R CNN
F1 "eSim_MOS_P" 50 150 50 H V R CNN
F2 "" 250 100 29 H V C CNN
F3 "" 50 0 60 H V C CNN
ALIAS mosfet_p
DRAW
C 100 0 111 0 1 10 N
P 2 0 1 0 80 -70 150 -70 N
P 2 0 1 10 80 -50 80 -90 N
P 2 0 1 0 80 0 150 0 N
P 2 0 1 10 80 20 80 -20 N
P 2 0 1 0 80 70 150 70 N
P 2 0 1 10 80 90 80 50 N
P 2 0 1 0 150 -70 150 -100 N
P 2 0 1 0 150 100 150 70 N
P 3 0 1 10 60 75 60 -75 60 -75 N
P 3 0 1 0 150 0 250 0 250 -50 N
P 4 0 1 0 140 0 100 -15 100 15 140 0 F
X D 1 150 200 100 D 50 50 1 1 P
X G 2 -150 0 210 R 50 50 1 1 P
X S 3 150 -200 100 U 50 50 1 1 P
X B 4 250 -150 100 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# eSim_R
#
DEF eSim_R R 0 0 N Y 1 F N
F0 "R" 50 130 50 H V C CNN
F1 "eSim_R" 50 -50 50 H V C CNN
F2 "" 50 -20 30 H V C CNN
F3 "" 50 50 30 V V C CNN
ALIAS resistor
$FPLIST
R_*
Resistor_*
$ENDFPLIST
DRAW
S 150 10 -50 90 0 1 10 N
X ~ 1 -100 50 50 R 60 60 1 1 P
X ~ 2 200 50 50 L 60 60 1 1 P
ENDDRAW
ENDDEF
#
#End Library
38 changes: 38 additions & 0 deletions library/SubcircuitLibrary/ICM7555/ICM7555.cir
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -0,0 +1,38 @@
* D:\FOSSEE\eSim\library\SubcircuitLibrary\ICM7555\ICM7555.cir

* EESchema Netlist Version 1.1 (Spice format) creation date: 06/11/25 10:14:45

* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0

* Sheet Name: /
M2 /8 Net-_M2-Pad2_ Net-_M1-Pad1_ /8 eSim_MOS_P
M3 /8 Net-_M2-Pad2_ Net-_M2-Pad2_ /8 eSim_MOS_P
M1 Net-_M1-Pad1_ /6 Net-_I1-Pad1_ Net-_I1-Pad1_ eSim_MOS_N
M4 Net-_M2-Pad2_ /5 Net-_I1-Pad1_ Net-_I1-Pad1_ eSim_MOS_N
R1 /8 /5 100k
R2 /5 Net-_M5-Pad2_ 100k
R3 Net-_M5-Pad2_ /1 100k
M5 Net-_I2-Pad2_ Net-_M5-Pad2_ Net-_M5-Pad3_ Net-_I2-Pad2_ eSim_MOS_P
M8 Net-_I2-Pad2_ /2 Net-_M10-Pad2_ Net-_I2-Pad2_ eSim_MOS_P
M6 Net-_M5-Pad3_ Net-_M5-Pad3_ /1 /1 eSim_MOS_N
M7 Net-_M10-Pad2_ Net-_M5-Pad3_ /1 /1 eSim_MOS_N
M11 /8 Net-_M1-Pad1_ Net-_M10-Pad1_ /8 eSim_MOS_P
M10 Net-_M10-Pad1_ Net-_M10-Pad2_ /1 /1 eSim_MOS_N
M9 Net-_M10-Pad2_ Net-_M9-Pad2_ /1 /1 eSim_MOS_N
U2 /4 Net-_U2-Pad2_ d_inverter
U3 Net-_U11-Pad2_ Net-_U3-Pad2_ Net-_U3-Pad3_ d_nor
U5 Net-_U3-Pad3_ Net-_U10-Pad1_ d_inverter
U4 Net-_U3-Pad3_ Net-_U4-Pad2_ d_inverter
U6 Net-_U10-Pad1_ /3 d_inverter
M12 /7 Net-_M12-Pad2_ /1 /1 eSim_MOS_N
U1 /1 /2 /3 /4 /5 /6 /7 /8 PORT
U8 Net-_U2-Pad2_ Net-_M9-Pad2_ dac_bridge_1
U7 Net-_M9-Pad2_ Net-_U3-Pad2_ adc_bridge_1
U10 Net-_U10-Pad1_ Net-_M12-Pad2_ dac_bridge_1
U9 Net-_U4-Pad2_ Net-_M10-Pad1_ dac_bridge_1
U11 Net-_M10-Pad1_ Net-_U11-Pad2_ adc_bridge_1
I1 Net-_I1-Pad1_ /1 120u
I2 /8 Net-_I2-Pad2_ 120u

.end
71 changes: 71 additions & 0 deletions library/SubcircuitLibrary/ICM7555/ICM7555.cir.out
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -0,0 +1,71 @@
* d:\fossee\esim\library\subcircuitlibrary\icm7555\icm7555.cir

.include PMOS-0.5um.lib
.include NMOS-0.5um.lib
m2 /8 net-_m2-pad2_ net-_m1-pad1_ /8 mos_p W=100u L=100u M=1
m3 /8 net-_m2-pad2_ net-_m2-pad2_ /8 mos_p W=100u L=100u M=1
m1 net-_m1-pad1_ /6 net-_i1-pad1_ net-_i1-pad1_ mos_n W=100u L=100u M=1
m4 net-_m2-pad2_ /5 net-_i1-pad1_ net-_i1-pad1_ mos_n W=100u L=100u M=1
r1 /8 /5 100k
r2 /5 net-_m5-pad2_ 100k
r3 net-_m5-pad2_ /1 100k
m5 net-_i2-pad2_ net-_m5-pad2_ net-_m5-pad3_ net-_i2-pad2_ mos_p W=100u L=100u M=1
m8 net-_i2-pad2_ /2 net-_m10-pad2_ net-_i2-pad2_ mos_p W=100u L=100u M=1
m6 net-_m5-pad3_ net-_m5-pad3_ /1 /1 mos_n W=100u L=100u M=1
m7 net-_m10-pad2_ net-_m5-pad3_ /1 /1 mos_n W=100u L=100u M=1
m11 /8 net-_m1-pad1_ net-_m10-pad1_ /8 mos_p W=100u L=100u M=1
m10 net-_m10-pad1_ net-_m10-pad2_ /1 /1 mos_n W=100u L=100u M=1
m9 net-_m10-pad2_ net-_m9-pad2_ /1 /1 mos_n W=100u L=100u M=1
* u2 /4 net-_u2-pad2_ d_inverter
* u3 net-_u11-pad2_ net-_u3-pad2_ net-_u3-pad3_ d_nor
* u5 net-_u3-pad3_ net-_u10-pad1_ d_inverter
* u4 net-_u3-pad3_ net-_u4-pad2_ d_inverter
* u6 net-_u10-pad1_ /3 d_inverter
m12 /7 net-_m12-pad2_ /1 /1 mos_n W=100u L=100u M=1
* u1 /1 /2 /3 /4 /5 /6 /7 /8 port
* u8 net-_u2-pad2_ net-_m9-pad2_ dac_bridge_1
* u7 net-_m9-pad2_ net-_u3-pad2_ adc_bridge_1
* u10 net-_u10-pad1_ net-_m12-pad2_ dac_bridge_1
* u9 net-_u4-pad2_ net-_m10-pad1_ dac_bridge_1
* u11 net-_m10-pad1_ net-_u11-pad2_ adc_bridge_1
i1 net-_i1-pad1_ /1 dc 30ua
i2 /8 net-_i2-pad2_ dc 30ua
a1 /4 net-_u2-pad2_ u2
a2 [net-_u11-pad2_ net-_u3-pad2_ ] net-_u3-pad3_ u3
a3 net-_u3-pad3_ net-_u10-pad1_ u5
a4 net-_u3-pad3_ net-_u4-pad2_ u4
a5 net-_u10-pad1_ /3 u6
a6 [net-_u2-pad2_ ] [net-_m9-pad2_ ] u8
a7 [net-_m9-pad2_ ] [net-_u3-pad2_ ] u7
a8 [net-_u10-pad1_ ] [net-_m12-pad2_ ] u10
a9 [net-_u4-pad2_ ] [net-_m10-pad1_ ] u9
a10 [net-_m10-pad1_ ] [net-_u11-pad2_ ] u11
* Schematic Name: d_inverter, NgSpice Name: d_inverter
.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_nor, NgSpice Name: d_nor
.model u3 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_inverter, NgSpice Name: d_inverter
.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_inverter, NgSpice Name: d_inverter
.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_inverter, NgSpice Name: d_inverter
.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge
.model u8 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge
.model u7 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge
.model u10 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge
.model u9 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge
.model u11 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
.tran 1e-00 9e-00 0e-00

* Control Statements
.control
run
print allv > plot_data_v.txt
print alli > plot_data_i.txt
.endc
.end
73 changes: 73 additions & 0 deletions library/SubcircuitLibrary/ICM7555/ICM7555.pro
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -0,0 +1,73 @@
update=22/05/2015 07:44:53
version=1
last_client=kicad
[general]
version=1
RootSch=
BoardNm=
[pcbnew]
version=1
LastNetListRead=
UseCmpFile=1
PadDrill=0.600000000000
PadDrillOvalY=0.600000000000
PadSizeH=1.500000000000
PadSizeV=1.500000000000
PcbTextSizeV=1.500000000000
PcbTextSizeH=1.500000000000
PcbTextThickness=0.300000000000
ModuleTextSizeV=1.000000000000
ModuleTextSizeH=1.000000000000
ModuleTextSizeThickness=0.150000000000
SolderMaskClearance=0.000000000000
SolderMaskMinWidth=0.000000000000
DrawSegmentWidth=0.200000000000
BoardOutlineThickness=0.100000000000
ModuleOutlineThickness=0.150000000000
[cvpcb]
version=1
NetIExt=net
[eeschema]
version=1
LibDir=
[eeschema/libraries]
LibName1=adc-dac
LibName2=memory
LibName3=xilinx
LibName4=microcontrollers
LibName5=dsp
LibName6=microchip
LibName7=analog_switches
LibName8=motorola
LibName9=texas
LibName10=intel
LibName11=audio
LibName12=interface
LibName13=digital-audio
LibName14=philips
LibName15=display
LibName16=cypress
LibName17=siliconi
LibName18=opto
LibName19=atmel
LibName20=contrib
LibName21=power
LibName22=eSim_Plot
LibName23=transistors
LibName24=conn
LibName25=eSim_User
LibName26=regul
LibName27=74xx
LibName28=cmos4000
LibName29=eSim_Analog
LibName30=eSim_Devices
LibName31=eSim_Digital
LibName32=eSim_Hybrid
LibName33=eSim_Miscellaneous
LibName34=eSim_Power
LibName35=eSim_Sources
LibName36=eSim_Subckt
LibName37=eSim_Nghdl
LibName38=eSim_Ngveri
LibName39=eSim_SKY130
LibName40=eSim_SKY130_Subckts
Loading