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Merge pull request #2290 from Sonicadvance1/new_arm_emitter
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Create a new ARM64 Emitter and move JIT over to it.
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Sonicadvance1 authored Jan 5, 2023
2 parents 12b866c + 8a38999 commit ec55ecd
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Showing 41 changed files with 31,459 additions and 6,320 deletions.
4 changes: 4 additions & 0 deletions External/FEXCore/CMakeLists.txt
Original file line number Diff line number Diff line change
Expand Up @@ -82,3 +82,7 @@ add_subdirectory(Source/)
install (DIRECTORY include/FEXCore ${CMAKE_BINARY_DIR}/include/FEXCore
DESTINATION include
COMPONENT Development)

if (BUILD_TESTS)
add_subdirectory(unittests/)
endif()
7 changes: 3 additions & 4 deletions External/FEXCore/Source/Interface/Core/ArchHelpers/Arm64.cpp
Original file line number Diff line number Diff line change
@@ -1,7 +1,6 @@
#include "Interface/Core/ArchHelpers/Arm64.h"
#include "Interface/Core/ArchHelpers/MContext.h"

#include <aarch64/cpu-aarch64.h>
#include "Interface/Core/ArchHelpers/CodeEmitter/Buffer.h"

#include <FEXCore/Utils/EnumUtils.h>
#include <FEXCore/Utils/LogManager.h>
Expand Down Expand Up @@ -572,7 +571,7 @@ bool HandleAtomicVectorStore(void *_ucontext, void *_info, uint32_t Instr) {
PC[1] = STP;
PC[2] = DMB;
// Back up one instruction and have another go
vixl::aarch64::CPU::EnsureIAndDCacheCoherency(&PC[0], 16);
FEXCore::ARMEmitter::Buffer::ClearICache(&PC[0], 16);
return true;
}
}
Expand Down Expand Up @@ -2311,7 +2310,7 @@ bool HandleSIGBUS(bool ParanoidTSO, int Signal, void *info, void *ucontext) {
return false;
}

vixl::aarch64::CPU::EnsureIAndDCacheCoherency(&PC[-1], 16);
FEXCore::ARMEmitter::Buffer::ClearICache(&PC[-1], 16);
return true;
}
return false;
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