Home

This C project is a cache simulation of a CPU containing L1D, L1I and L2 caches. It takes an image of memory and a memory trace as input, simulates the hit/miss behavior of a cache memory on this trace, and outputs the total number of hits, misses and evictions for each cache type along with the content of each cache at the end.

It takes command-line arguments about the information of wanted CPU caches. Detailed explanations are in cachelab.pdf file. Also I included the RAM.dat image file.

If you are reading this file, most probably you know how to compile this C program and execute it. But if you don't know it, visit this page to learn how to run it.