nrf: Add nrf9160 base support.

This patch add basic building blocks for nrf9P60.

It also includes a secure bootloader which forwards all
possible peripherals that are user selectable to become
non-secure. After configuring Flash, RAM and peripherals
the secure bootloader will jump to the non-secure domain
where MicroPython is placed.

The minimum size of a secure boot has to be a flash
block of 32Kb, hence why the linker scripts are
offsetting the main application this much.

The RAM offset is set to 128K, to allow for later
integration of Nordic Semiconductor's BSD socket
library which reserves the range 0x20010000 - 0x2001FFFF.

ports/nrf/Makefile

@@ -82,13 +82,18 @@ else ifeq ($(MCU_SUB_VARIANT),nrf52832)
 else ifeq ($(MCU_SUB_VARIANT),nrf52840)
 	SYSTEM_C_SRC += $(addprefix lib/nrfx/mdk/, system_nrf52840.c)
 	# Do not pass MCU_VARIANT_UPPER flag, as NRF52 defines NRF52832 only.
+else ifeq ($(MCU_SUB_VARIANT),nrf9160)
+        SYSTEM_C_SRC += $(addprefix lib/nrfx/mdk/, system_nrf9160.c)
+        NRF_DEFINES += -D$(MCU_VARIANT_UPPER)
 endif
 
 NRF_DEFINES += -D$(MCU_SUB_VARIANT_UPPER)
 NRF_DEFINES += -DCONFIG_GPIO_AS_PINRESET
 
 CFLAGS_CORTEX_M = -mthumb -mabi=aapcs -fsingle-precision-constant -Wdouble-promotion
 
+CFLAGS_MCU_m33 = $(CFLAGS_CORTEX_M) -mcpu=cortex-m33 -march=armv8-m.main+dsp -mcmse -mfpu=fpv5-sp-d16 -mfloat-abi=hard
+
 CFLAGS_MCU_m4 = $(CFLAGS_CORTEX_M) -mtune=cortex-m4 -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard
 
 CFLAGS_MCU_m0 = $(CFLAGS_CORTEX_M) -fshort-enums -mtune=cortex-m0 -mcpu=cortex-m0 -mfloat-abi=soft -fno-builtin
@@ -125,10 +130,31 @@ endif
 LIBS = \
 
 ifeq ($(MCU_VARIANT), nrf52)
-LIBGCC_FILE_NAME = $(shell $(CC) $(CFLAGS) -print-libgcc-file-name)
 
-LIBS += -L $(dir $(LIBGCC_FILE_NAME)) -lgcc
+SRC_LIB += $(addprefix lib/,\
+        libm/math.c \
+        libm/fmodf.c \
+        libm/nearbyintf.c \
+        libm/ef_sqrt.c \
+        libm/kf_rem_pio2.c \
+        libm/kf_sin.c \
+        libm/kf_cos.c \
+        libm/kf_tan.c \
+        libm/ef_rem_pio2.c \
+        libm/sf_sin.c \
+        libm/sf_cos.c \
+        libm/sf_tan.c \
+        libm/sf_frexp.c \
+        libm/sf_modf.c \
+        libm/sf_ldexp.c \
+        libm/asinfacosf.c \
+        libm/atanf.c \
+        libm/atan2f.c \
+	)
+
+endif
 
+ifeq ($(MCU_VARIANT), nrf91)
 
 SRC_LIB += $(addprefix lib/,\
         libm/math.c \
@@ -149,7 +175,14 @@ SRC_LIB += $(addprefix lib/,\
         libm/asinfacosf.c \
         libm/atanf.c \
         libm/atan2f.c \
-	)
+        )
+
+SRC_NRFX += $(addprefix lib/nrfx/drivers/src/,\
+        nrfx_uarte.c \
+        nrfx_twim.c \
+        )
+
+include drivers/secureboot/secureboot.mk
 
 endif
 
@@ -271,21 +304,28 @@ FROZEN_MPY_PY_FILES := $(shell find -L $(FROZEN_MPY_DIR) -type f -name '*.py')
 FROZEN_MPY_MPY_FILES := $(addprefix $(BUILD)/,$(FROZEN_MPY_PY_FILES:.py=.mpy))
 endif
 
+LIBGCC_FILE_NAME = $(shell $(CC) $(CFLAGS) -print-libgcc-file-name)
+LIBS += -L $(dir $(LIBGCC_FILE_NAME)) -lgcc
+
 OBJ += $(PY_O) $(addprefix $(BUILD)/, $(SRC_C:.c=.o))
-OBJ += $(addprefix $(BUILD)/, $(SRC_LIB:.c=.o))
 OBJ += $(addprefix $(BUILD)/, $(SRC_MOD:.c=.o))
 OBJ += $(addprefix $(BUILD)/, $(SRC_NRFX:.c=.o))
 OBJ += $(addprefix $(BUILD)/, $(SRC_NRFX_HAL:.c=.o))
 OBJ += $(addprefix $(BUILD)/, $(DRIVERS_SRC_C:.c=.o))
 OBJ += $(addprefix $(BUILD)/, $(SYSTEM_C_SRC:.c=.o))
+OBJ += $(addprefix $(BUILD)/, $(SRC_LIB:.c=.o))
 OBJ += $(BUILD)/pins_gen.o
 
 $(BUILD)/$(FATFS_DIR)/ff.o: COPT += -Os
 $(filter $(PY_BUILD)/../extmod/vfs_fat_%.o, $(PY_O)): COPT += -Os
 
 .PHONY: all flash deploy sd binary hex
 
+ifeq ($(MCU_VARIANT), nrf91)
+all: binary hex secureboot
+else
 all: binary hex
+endif
 
 OUTPUT_FILENAME = firmware
 
@@ -305,10 +345,21 @@ FLASHER ?=
 
 ifeq ($(FLASHER),)
 
+ifeq ($(MCU_VARIANT), nrf91)
+
+deploy: $(BUILD)/$(OUTPUT_FILENAME).hex $(BUILD)/secureboot.hex
+	nrfjprog --program $(BUILD)/secureboot.hex --sectorerase -f $(MCU_VARIANT)
+	nrfjprog --program $(BUILD)/$(OUTPUT_FILENAME).hex --sectorerase -f $(MCU_VARIANT)
+	nrfjprog --reset -f $(MCU_VARIANT)
+
+else
+
 deploy: $(BUILD)/$(OUTPUT_FILENAME).hex
 	nrfjprog --program $< --sectorerase -f $(MCU_VARIANT)
 	nrfjprog --reset -f $(MCU_VARIANT)
 
+endif
+
 sd: $(BUILD)/$(OUTPUT_FILENAME).hex
 	nrfjprog --eraseall -f $(MCU_VARIANT)
 	nrfjprog --program $(SOFTDEV_HEX) -f $(MCU_VARIANT)

ports/nrf/boards/nrf9160_1M_256k.ld

@@ -0,0 +1,13 @@
+/*
+    GNU linker script for NRF9160 NS
+*/
+
+_flash_size = 1M;
+_ram_size   = 256K;
+_sd_size = 0x00008000;
+_sd_ram  = 0x00020000;
+_fs_size = 80K;
+
+/* produce a link error if there is not this amount of RAM for these sections */
+_stack_size = 32K;
+_minimum_heap_size = 64K;

ports/nrf/boards/nrf9160_1M_256k_secure.ld

@@ -0,0 +1,6 @@
+/* Specify the memory areas */
+MEMORY
+{
+    FLASH_TEXT (rx) : ORIGIN = 0x00000000,     LENGTH = 32K
+    RAM (xrw)       : ORIGIN = 0x20000000,     LENGTH = 64K
+}

ports/nrf/boards/nrf91_prefix.c

@@ -0,0 +1,29 @@
+// nrf91_prefix.c becomes the initial portion of the generated pins file.
+
+#include <stdio.h>
+
+#include "py/obj.h"
+#include "py/mphal.h"
+#include "pin.h"
+
+#define AF(af_idx, af_fn, af_unit, af_type, af_ptr) \
+{ \
+    { &pin_af_type }, \
+    .name = MP_QSTR_AF ## af_idx ## _ ## af_fn ## af_unit, \
+    .idx = (af_idx), \
+    .fn = AF_FN_ ## af_fn, \
+    .unit = (af_unit), \
+    .type = AF_PIN_TYPE_ ## af_fn ## _ ## af_type, \
+    .af_fn = (af_ptr) \
+}
+
+#define PIN(p_pin, p_af, p_adc_num, p_adc_channel) \
+{ \
+    { &pin_type }, \
+    .name = MP_QSTR_P ## p_pin, \
+    .pin = (p_pin), \
+    .num_af = (sizeof(p_af) / sizeof(pin_af_obj_t)), \
+    .af = p_af, \
+    .adc_num = p_adc_num, \
+    .adc_channel = p_adc_channel, \
+}