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cubenode: specify ethernet pin names #44

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2 changes: 1 addition & 1 deletion cubenode/pin-descriptions.md
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Expand Up @@ -6,5 +6,5 @@ Depending on the CubeNode version, the IMU may not be available. 

<figure><img src="../.gitbook/assets/CubeNode Pin descriptions.jpg" alt=""><figcaption></figcaption></figure>

<table><thead><tr><th width="137">Pin Number</th><th width="108">Pin Type</th><th width="134">Pin Name</th><th width="157">Function</th><th>Additional Functions</th></tr></thead><tbody><tr><td>1</td><td>I/O</td><td>CAN1_L</td><td>CAN1_L</td><td></td></tr><tr><td>2</td><td>I/O</td><td>CAN1_H</td><td>CAN1_H</td><td></td></tr><tr><td>3</td><td>I/O</td><td>PE1</td><td>UART8_TX</td><td>EVENTOUT</td></tr><tr><td>4</td><td>I/O</td><td>PE0</td><td>UART8_RX</td><td>EVENTOUT</td></tr><tr><td>5</td><td>I/O</td><td>PB8</td><td>I2C1_SCL</td><td>TIM16_CH1,TIM4_CH3,UART4_RX,EVENTOUT</td></tr><tr><td>6</td><td>I/O</td><td>PB7</td><td>I2C1_SDA</td><td>TIM17_CH1N,TIM4_CH2,USART1_RX,EVENTOUT</td></tr><tr><td>7</td><td>I/O</td><td>PC10</td><td>SPI3_SCK</td><td>USART3_TX,UART4_TX,EVENTOUT</td></tr><tr><td>8</td><td>I/O</td><td>PC11</td><td>SPI3_MISO</td><td>USART3_RX,UART4_RX,EVENTOUT</td></tr><tr><td>9</td><td>I/O</td><td>PC12</td><td>SPI3_MOSI</td><td>UART5_TX,EVENTOUT</td></tr><tr><td>10</td><td>I/O</td><td>PA10/PA8</td><td>SPI3_CS</td><td>TIM1_CH1,I2C3_SCL,EVENTOUT</td></tr><tr><td>11</td><td></td><td></td><td><strong>Reserved Don’t Use</strong></td><td></td></tr><tr><td>12</td><td></td><td></td><td><strong>Reserved Don’t Use</strong></td><td></td></tr><tr><td>13</td><td>P</td><td>VDD_3V3</td><td>VDD_3V3</td><td></td></tr><tr><td>14</td><td>I/O</td><td>CAN2_L</td><td>CAN2_L</td><td></td></tr><tr><td>15</td><td>I/O</td><td>CAN2_H</td><td>CAN2_H</td><td></td></tr><tr><td>16</td><td>I/O</td><td>PA14</td><td>SWCLK</td><td></td></tr><tr><td>17</td><td>I/O</td><td>PA13</td><td>SWDIO</td><td></td></tr><tr><td>18</td><td>I</td><td>NRST</td><td>NRST</td><td></td></tr><tr><td>19</td><td>I</td><td>BOOT0</td><td>BOOT0</td><td></td></tr><tr><td>20</td><td>I/O</td><td>PE2</td><td>GPIO_PE2</td><td>SPI4_SCK,EVENTOUT</td></tr><tr><td>21</td><td>I/O</td><td>PE10</td><td>GPIO_PE10</td><td>TIM1_CH2N,EVENTOUT</td></tr><tr><td>22</td><td>I/O</td><td>PE8</td><td>UART7_TX</td><td>TIM1_CH1N,EVENTOUT</td></tr><tr><td>23</td><td>I/O</td><td>PE7</td><td>UART7_RX</td><td>EVENTOUT.</td></tr><tr><td>24</td><td>P</td><td>GND</td><td>GND</td><td></td></tr><tr><td>25</td><td>I/O</td><td>PF3</td><td>ADC3_INP5</td><td>EVENTOUT</td></tr><tr><td>26</td><td>I/O</td><td>PF5</td><td>ADC3_INP4</td><td>EVENTOUT</td></tr><tr><td>27</td><td>I/O</td><td>PC3_C</td><td>ADC3_INP1</td><td>EVENTOUT</td></tr><tr><td>28</td><td>I/O</td><td>PC2_C</td><td>ADC3_INP0</td><td>SPI2_MISO,ADC3_INN1,EVENTOUT</td></tr><tr><td>29</td><td>P</td><td>GND</td><td>GND</td><td></td></tr><tr><td>30</td><td>I/O</td><td>PC9</td><td>TIM8_CH4</td><td>TIM3_CH4,I2C3_SDA,EVENTOUT</td></tr><tr><td>31</td><td>I/O</td><td>PC8</td><td>TIM8_CH3</td><td>TIM3_CH3,EVENTOUT</td></tr><tr><td>32</td><td>I/O</td><td>PD15</td><td>TIM4_CH4</td><td>EVENTOUT</td></tr><tr><td>33</td><td>I/O</td><td>PD14</td><td>TIM4_CH3</td><td>EVENTOUT</td></tr><tr><td>34</td><td>I/O</td><td>PD13</td><td>TIM4_CH2</td><td>I2C4_SDA,EVENTOUT</td></tr><tr><td>35</td><td>I/O</td><td>PD12</td><td>TIM4_CH1</td><td>I2C4_SCL,EVENTOUT</td></tr><tr><td>36</td><td>P</td><td>GND</td><td>GND</td><td></td></tr><tr><td>37</td><td>I/O</td><td>PF4</td><td>ADC3_INP9</td><td>ADC3_INN5,ADC3_INP9,EVENTOUT</td></tr><tr><td>38</td><td>I/O</td><td>PF14</td><td>ADC2_INP6</td><td>I2C4_SCL,ADC2_INN2,ADC2_INP6,EVENTOUT</td></tr><tr><td>39</td><td>I/O</td><td>PF13</td><td>ADC2_INP2</td><td>EVENTOUT</td></tr><tr><td>40</td><td></td><td></td><td><strong>Reserved Don’t Use</strong></td><td></td></tr><tr><td>41</td><td></td><td></td><td><strong>Reserved Don’t Use</strong></td><td></td></tr><tr><td>42</td><td>P</td><td>GND</td><td>GND</td><td></td></tr><tr><td>43</td><td>I/O</td><td>PC7</td><td>TIM8_CH2</td><td>USART6_RX,TIM3_CH2,EVENTOUT</td></tr><tr><td>44</td><td>I/O</td><td>PC6</td><td>TIM8_CH1</td><td>USART6_TX,TIM3_CH1,EVENTOUT</td></tr><tr><td>45</td><td>I/O</td><td>PB1</td><td>TIM3_CH4</td><td>TIM1_CH3N,TIM8_CH3N,TIM8_CH3N,EVENTOUT</td></tr><tr><td>46</td><td>I/O</td><td>PB0</td><td>TIM3_CH3</td><td>TIM1_CH2N,TIM8_CH2N,ADC12_INN5,ADC12_INP9,EVENTOUT</td></tr><tr><td>47</td><td>I/O</td><td>PE6</td><td>TIM15_CH2</td><td>SPI4_MOSI,EVENTOUT</td></tr><tr><td>48</td><td></td><td></td><td><strong>Reserved Don’t Use</strong></td><td></td></tr><tr><td>49</td><td>P</td><td>GND</td><td>GND</td><td></td></tr><tr><td>50</td><td>I/O</td><td>PA5</td><td>ADC1_INP19</td><td>TIM2_CH1,TIM8_CH1N,SPI1_SCK,EVENTOUT</td></tr><tr><td>51</td><td>I/O</td><td>PA4</td><td>ADC1_INP18</td><td>DAC1_OUT1,EVENTOUT</td></tr><tr><td>52</td><td></td><td></td><td><strong>Reserved Don’t Use</strong></td><td></td></tr><tr><td>53</td><td>I/O</td><td>PC0</td><td>ADC1_INP10</td><td>EVENTOUT</td></tr><tr><td>54</td><td>P</td><td>GND</td><td>GND</td><td></td></tr><tr><td>55</td><td>I/O</td><td>PA3</td><td>TIM5_CH4</td><td>TIM2_CH4,TIM15_CH2,USART2_RX,ADC12_INP15,EVENTOUT</td></tr><tr><td>56</td><td></td><td></td><td><strong>Reserved Don’t Use</strong></td><td></td></tr><tr><td>57</td><td>I/O</td><td>PE5</td><td>TIM15_CH1</td><td>SPI4_MISO,EVENTOUT</td></tr><tr><td>58</td><td>I/O</td><td>PB10</td><td>TIM2_CH3</td><td>I2C2_SCL,SPI2_SCK,USART3_TX,EVENTOUT</td></tr><tr><td>59</td><td></td><td></td><td><strong>Reserved Don’t Use</strong></td><td></td></tr><tr><td>60</td><td>I/O</td><td>PA15</td><td>TIM2_CH1</td><td>EVENTOUT</td></tr><tr><td>61</td><td>P</td><td>GND</td><td>GND</td><td></td></tr><tr><td>62</td><td>I/O</td><td>PF12</td><td>ADC1_INP6</td><td>ADC1_INN2,EVENTOUT</td></tr><tr><td>63</td><td></td><td></td><td><strong>Reserved Don’t Use</strong></td><td></td></tr><tr><td>64</td><td>I/O</td><td>PA6</td><td>ADC1_INP3</td><td>TIM3_CH1,SPI1_MISO,TIM13_CH1,EVENTOUT</td></tr><tr><td>65</td><td>I/O</td><td>PF11</td><td>ADC1_INP2</td><td>ADC1_INP2,EVENTOUT</td></tr><tr><td>66</td><td>P</td><td>GND</td><td>GND</td><td></td></tr><tr><td>67</td><td></td><td></td><td><strong>Reserved Don’t Use</strong></td><td></td></tr><tr><td>68</td><td>I/O</td><td>PA0</td><td>TIM5_CH1</td><td>TIM2_CH1,UART4_TX,ADC1_INP16,EVENTOUT</td></tr><tr><td>69</td><td>I/O</td><td>PE14</td><td>TIM1_CH4</td><td>SPI4_MOSI,EVENTOUT</td></tr><tr><td>70</td><td>I/O</td><td>PE13</td><td>TIM1_CH3</td><td>SPI4_MISO,EVENTOUT</td></tr><tr><td>71</td><td>I/O</td><td>PE11</td><td>TIM1_CH2</td><td>EVENTOUT</td></tr><tr><td>72</td><td>I/O</td><td>PE9</td><td>TIM1_CH1</td><td>EVENTOUT</td></tr><tr><td>73</td><td>P</td><td>GND</td><td>GND</td><td></td></tr><tr><td>74</td><td>P</td><td>GND</td><td>GND</td><td></td></tr><tr><td>75</td><td>I/O</td><td>PA12</td><td>OTG_FS_DP</td><td>UART4_TX,EVENTOUT</td></tr><tr><td>76</td><td>I/O</td><td>PA11</td><td>OTG_FS_DM</td><td>TIM1_CH4,UART4_RX,EVENTOUT</td></tr><tr><td>77</td><td>P</td><td>PA9</td><td>VBUS</td><td></td></tr><tr><td>78</td><td>P</td><td>VDD_5V</td><td>VDD_5V</td><td></td></tr><tr><td>79</td><td>I/O</td><td>ETHERNET_TX-</td><td>ETHERNET_TX-</td><td></td></tr><tr><td>80</td><td>I/O</td><td>ETHERNET_TX+</td><td>ETHERNET_TX+</td><td></td></tr><tr><td>81</td><td>I/O</td><td>ETHERNET_RX-</td><td>ETHERNET_RX-</td><td></td></tr><tr><td>82</td><td>I/O</td><td>ETHERNET_RX+</td><td>ETHERNET_RX+</td><td></td></tr><tr><td>83-84</td><td>P</td><td>GND</td><td>GND</td><td></td></tr><tr><td>85-95</td><td></td><td></td><td><strong>Reserved Don’t Use</strong></td><td></td></tr><tr><td>96-97</td><td>P</td><td>GND</td><td>GND</td><td></td></tr><tr><td>98-100</td><td></td><td></td><td><strong>Reserved Don’t Use</strong></td><td></td></tr><tr><td>101</td><td>I/O</td><td>PB15</td><td>SDMMC2_D1</td><td>TIM1_CH3N,TIM12_CH2,TIM8_CH3N,USART1_RX,OTG_HS_DP,EVENTOUT</td></tr><tr><td>102</td><td>I/O</td><td>PB14</td><td>SDMMC2_D0</td><td>TIM1_CH2N,TIM12_CH1,TIM8,CH2N,USART1_TX,SPI2_MISO,OTG_HS_DM,EVENTOUT</td></tr><tr><td>103-105</td><td></td><td></td><td><strong>Reserved Don’t Use</strong></td><td></td></tr><tr><td>106</td><td>I/O</td><td>PB3</td><td>SDMMC2_D2</td><td>TIM2_CH2,SPI1_SCK,EVENTOUT</td></tr><tr><td>107</td><td>I/O</td><td>PB4</td><td>SDMMC2_D3</td><td>TIM3_CH1,SPI1_MISO,EVENTOUT</td></tr><tr><td>108-109</td><td></td><td></td><td><strong>Reserved Don’t Use</strong></td><td></td></tr><tr><td>110</td><td>I/O</td><td>PD6</td><td>SDMMC2_CK</td><td>USART2_RX,EVENTOUT</td></tr><tr><td>111</td><td>I/O</td><td>PD7</td><td>SDMMC2_CMD</td><td>SPI1_MOSI,EVENTOUT</td></tr></tbody></table>
<table><thead><tr><th width="137">Pin Number</th><th width="108">Pin Type</th><th width="134">Pin Name</th><th width="157">Function</th><th>Additional Functions</th></tr></thead><tbody><tr><td>1</td><td>I/O</td><td>CAN1_L</td><td>CAN1_L</td><td></td></tr><tr><td>2</td><td>I/O</td><td>CAN1_H</td><td>CAN1_H</td><td></td></tr><tr><td>3</td><td>I/O</td><td>PE1</td><td>UART8_TX</td><td>EVENTOUT</td></tr><tr><td>4</td><td>I/O</td><td>PE0</td><td>UART8_RX</td><td>EVENTOUT</td></tr><tr><td>5</td><td>I/O</td><td>PB8</td><td>I2C1_SCL</td><td>TIM16_CH1,TIM4_CH3,UART4_RX,EVENTOUT</td></tr><tr><td>6</td><td>I/O</td><td>PB7</td><td>I2C1_SDA</td><td>TIM17_CH1N,TIM4_CH2,USART1_RX,EVENTOUT</td></tr><tr><td>7</td><td>I/O</td><td>PC10</td><td>SPI3_SCK</td><td>USART3_TX,UART4_TX,EVENTOUT</td></tr><tr><td>8</td><td>I/O</td><td>PC11</td><td>SPI3_MISO</td><td>USART3_RX,UART4_RX,EVENTOUT</td></tr><tr><td>9</td><td>I/O</td><td>PC12</td><td>SPI3_MOSI</td><td>UART5_TX,EVENTOUT</td></tr><tr><td>10</td><td>I/O</td><td>PA10/PA8</td><td>SPI3_CS</td><td>TIM1_CH1,I2C3_SCL,EVENTOUT</td></tr><tr><td>11</td><td></td><td></td><td><strong>Reserved Don’t Use</strong></td><td></td></tr><tr><td>12</td><td></td><td></td><td><strong>Reserved Don’t Use</strong></td><td></td></tr><tr><td>13</td><td>P</td><td>VDD_3V3</td><td>VDD_3V3</td><td></td></tr><tr><td>14</td><td>I/O</td><td>CAN2_L</td><td>CAN2_L</td><td></td></tr><tr><td>15</td><td>I/O</td><td>CAN2_H</td><td>CAN2_H</td><td></td></tr><tr><td>16</td><td>I/O</td><td>PA14</td><td>SWCLK</td><td></td></tr><tr><td>17</td><td>I/O</td><td>PA13</td><td>SWDIO</td><td></td></tr><tr><td>18</td><td>I</td><td>NRST</td><td>NRST</td><td></td></tr><tr><td>19</td><td>I</td><td>BOOT0</td><td>BOOT0</td><td></td></tr><tr><td>20</td><td>I/O</td><td>PE2</td><td>GPIO_PE2</td><td>SPI4_SCK,EVENTOUT</td></tr><tr><td>21</td><td>I/O</td><td>PE10</td><td>GPIO_PE10</td><td>TIM1_CH2N,EVENTOUT</td></tr><tr><td>22</td><td>I/O</td><td>PE8</td><td>UART7_TX</td><td>TIM1_CH1N,EVENTOUT</td></tr><tr><td>23</td><td>I/O</td><td>PE7</td><td>UART7_RX</td><td>EVENTOUT.</td></tr><tr><td>24</td><td>P</td><td>GND</td><td>GND</td><td></td></tr><tr><td>25</td><td>I/O</td><td>PF3</td><td>ADC3_INP5</td><td>EVENTOUT</td></tr><tr><td>26</td><td>I/O</td><td>PF5</td><td>ADC3_INP4</td><td>EVENTOUT</td></tr><tr><td>27</td><td>I/O</td><td>PC3_C</td><td>ADC3_INP1</td><td>EVENTOUT</td></tr><tr><td>28</td><td>I/O</td><td>PC2_C</td><td>ADC3_INP0</td><td>SPI2_MISO,ADC3_INN1,EVENTOUT</td></tr><tr><td>29</td><td>P</td><td>GND</td><td>GND</td><td></td></tr><tr><td>30</td><td>I/O</td><td>PC9</td><td>TIM8_CH4</td><td>TIM3_CH4,I2C3_SDA,EVENTOUT</td></tr><tr><td>31</td><td>I/O</td><td>PC8</td><td>TIM8_CH3</td><td>TIM3_CH3,EVENTOUT</td></tr><tr><td>32</td><td>I/O</td><td>PD15</td><td>TIM4_CH4</td><td>EVENTOUT</td></tr><tr><td>33</td><td>I/O</td><td>PD14</td><td>TIM4_CH3</td><td>EVENTOUT</td></tr><tr><td>34</td><td>I/O</td><td>PD13</td><td>TIM4_CH2</td><td>I2C4_SDA,EVENTOUT</td></tr><tr><td>35</td><td>I/O</td><td>PD12</td><td>TIM4_CH1</td><td>I2C4_SCL,EVENTOUT</td></tr><tr><td>36</td><td>P</td><td>GND</td><td>GND</td><td></td></tr><tr><td>37</td><td>I/O</td><td>PF4</td><td>ADC3_INP9</td><td>ADC3_INN5,ADC3_INP9,EVENTOUT</td></tr><tr><td>38</td><td>I/O</td><td>PF14</td><td>ADC2_INP6</td><td>I2C4_SCL,ADC2_INN2,ADC2_INP6,EVENTOUT</td></tr><tr><td>39</td><td>I/O</td><td>PF13</td><td>ADC2_INP2</td><td>EVENTOUT</td></tr><tr><td>40</td><td></td><td></td><td><strong>Reserved Don’t Use</strong></td><td></td></tr><tr><td>41</td><td></td><td></td><td><strong>Reserved Don’t Use</strong></td><td></td></tr><tr><td>42</td><td>P</td><td>GND</td><td>GND</td><td></td></tr><tr><td>43</td><td>I/O</td><td>PC7</td><td>TIM8_CH2</td><td>USART6_RX,TIM3_CH2,EVENTOUT</td></tr><tr><td>44</td><td>I/O</td><td>PC6</td><td>TIM8_CH1</td><td>USART6_TX,TIM3_CH1,EVENTOUT</td></tr><tr><td>45</td><td>I/O</td><td>PB1</td><td>TIM3_CH4</td><td>TIM1_CH3N,TIM8_CH3N,TIM8_CH3N,EVENTOUT</td></tr><tr><td>46</td><td>I/O</td><td>PB0</td><td>TIM3_CH3</td><td>TIM1_CH2N,TIM8_CH2N,ADC12_INN5,ADC12_INP9,EVENTOUT</td></tr><tr><td>47</td><td>I/O</td><td>PE6</td><td>TIM15_CH2</td><td>SPI4_MOSI,EVENTOUT</td></tr><tr><td>48</td><td></td><td></td><td><strong>Reserved Don’t Use</strong></td><td></td></tr><tr><td>49</td><td>P</td><td>GND</td><td>GND</td><td></td></tr><tr><td>50</td><td>I/O</td><td>PA5</td><td>ADC1_INP19</td><td>TIM2_CH1,TIM8_CH1N,SPI1_SCK,EVENTOUT</td></tr><tr><td>51</td><td>I/O</td><td>PA4</td><td>ADC1_INP18</td><td>DAC1_OUT1,EVENTOUT</td></tr><tr><td>52</td><td></td><td></td><td><strong>Reserved Don’t Use</strong></td><td></td></tr><tr><td>53</td><td>I/O</td><td>PC0</td><td>ADC1_INP10</td><td>EVENTOUT</td></tr><tr><td>54</td><td>P</td><td>GND</td><td>GND</td><td></td></tr><tr><td>55</td><td>I/O</td><td>PA3</td><td>TIM5_CH4</td><td>TIM2_CH4,TIM15_CH2,USART2_RX,ADC12_INP15,EVENTOUT</td></tr><tr><td>56</td><td></td><td></td><td><strong>Reserved Don’t Use</strong></td><td></td></tr><tr><td>57</td><td>I/O</td><td>PE5</td><td>TIM15_CH1</td><td>SPI4_MISO,EVENTOUT</td></tr><tr><td>58</td><td>I/O</td><td>PB10</td><td>TIM2_CH3</td><td>I2C2_SCL,SPI2_SCK,USART3_TX,EVENTOUT</td></tr><tr><td>59</td><td></td><td></td><td><strong>Reserved Don’t Use</strong></td><td></td></tr><tr><td>60</td><td>I/O</td><td>PA15</td><td>TIM2_CH1</td><td>EVENTOUT</td></tr><tr><td>61</td><td>P</td><td>GND</td><td>GND</td><td></td></tr><tr><td>62</td><td>I/O</td><td>PF12</td><td>ADC1_INP6</td><td>ADC1_INN2,EVENTOUT</td></tr><tr><td>63</td><td></td><td></td><td><strong>Reserved Don’t Use</strong></td><td></td></tr><tr><td>64</td><td>I/O</td><td>PA6</td><td>ADC1_INP3</td><td>TIM3_CH1,SPI1_MISO,TIM13_CH1,EVENTOUT</td></tr><tr><td>65</td><td>I/O</td><td>PF11</td><td>ADC1_INP2</td><td>ADC1_INP2,EVENTOUT</td></tr><tr><td>66</td><td>P</td><td>GND</td><td>GND</td><td></td></tr><tr><td>67</td><td></td><td></td><td><strong>Reserved Don’t Use</strong></td><td></td></tr><tr><td>68</td><td>I/O</td><td>PA0</td><td>TIM5_CH1</td><td>TIM2_CH1,UART4_TX,ADC1_INP16,EVENTOUT</td></tr><tr><td>69</td><td>I/O</td><td>PE14</td><td>TIM1_CH4</td><td>SPI4_MOSI,EVENTOUT</td></tr><tr><td>70</td><td>I/O</td><td>PE13</td><td>TIM1_CH3</td><td>SPI4_MISO,EVENTOUT</td></tr><tr><td>71</td><td>I/O</td><td>PE11</td><td>TIM1_CH2</td><td>EVENTOUT</td></tr><tr><td>72</td><td>I/O</td><td>PE9</td><td>TIM1_CH1</td><td>EVENTOUT</td></tr><tr><td>73</td><td>P</td><td>GND</td><td>GND</td><td></td></tr><tr><td>74</td><td>P</td><td>GND</td><td>GND</td><td></td></tr><tr><td>75</td><td>I/O</td><td>PA12</td><td>OTG_FS_DP</td><td>UART4_TX,EVENTOUT</td></tr><tr><td>76</td><td>I/O</td><td>PA11</td><td>OTG_FS_DM</td><td>TIM1_CH4,UART4_RX,EVENTOUT</td></tr><tr><td>77</td><td>P</td><td>PA9</td><td>VBUS</td><td></td></tr><tr><td>78</td><td>P</td><td>VDD_5V</td><td>VDD_5V</td><td></td></tr><tr><td>79</td><td>I/O</td><td>PB12</td><td>ETHERNET_TX-</td><td></td></tr><tr><td>80</td><td>I/O</td><td>PB13</td><td>ETHERNET_TX+</td><td></td></tr><tr><td>81</td><td>I/O</td><td>PC4</td><td>ETHERNET_RX-</td><td></td></tr><tr><td>82</td><td>I/O</td><td>PC5</td><td>ETHERNET_RX+</td><td></td></tr><tr><td>83-84</td><td>P</td><td>GND</td><td>GND</td><td></td></tr><tr><td>85-95</td><td></td><td></td><td><strong>Reserved Don’t Use</strong></td><td></td></tr><tr><td>96-97</td><td>P</td><td>GND</td><td>GND</td><td></td></tr><tr><td>98-100</td><td></td><td></td><td><strong>Reserved Don’t Use</strong></td><td></td></tr><tr><td>101</td><td>I/O</td><td>PB15</td><td>SDMMC2_D1</td><td>TIM1_CH3N,TIM12_CH2,TIM8_CH3N,USART1_RX,OTG_HS_DP,EVENTOUT</td></tr><tr><td>102</td><td>I/O</td><td>PB14</td><td>SDMMC2_D0</td><td>TIM1_CH2N,TIM12_CH1,TIM8,CH2N,USART1_TX,SPI2_MISO,OTG_HS_DM,EVENTOUT</td></tr><tr><td>103-105</td><td></td><td></td><td><strong>Reserved Don’t Use</strong></td><td></td></tr><tr><td>106</td><td>I/O</td><td>PB3</td><td>SDMMC2_D2</td><td>TIM2_CH2,SPI1_SCK,EVENTOUT</td></tr><tr><td>107</td><td>I/O</td><td>PB4</td><td>SDMMC2_D3</td><td>TIM3_CH1,SPI1_MISO,EVENTOUT</td></tr><tr><td>108-109</td><td></td><td></td><td><strong>Reserved Don’t Use</strong></td><td></td></tr><tr><td>110</td><td>I/O</td><td>PD6</td><td>SDMMC2_CK</td><td>USART2_RX,EVENTOUT</td></tr><tr><td>111</td><td>I/O</td><td>PD7</td><td>SDMMC2_CMD</td><td>SPI1_MOSI,EVENTOUT</td></tr></tbody></table>