Upload PROLEADv3

Makefile

@@ -20,7 +20,7 @@
 INC_DIRS = inc
 
 # Source directories with the .c and .cpp files. Separate multiple directories with a space.
-TEST_SRC = "ut src/Hardware src/Util"
+TEST_SRC = "ut src/Software src/Hardware src/Util"
 DEBUG_SRC = src
 RELEASE_SRC = src
 
@@ -32,21 +32,25 @@ RELEASE_DIR = release
 DEBUG_DIR = debug
 TEST_DIR = test
 
+EXCLUDED_FILES := test/obj_test/ut/full/aes_rp_d1_ccode/aes_rp_d1_ccode_c.c
+
 # Compiler options
 INCLUDE_PYTHON3=`pkg-config --cflags python3-embed`
-C_RELEASE_FLAGS   = -Wall -Wextra -Wshadow -pedantic -fopenmp -O3 -fomit-frame-pointer -std=c11 $(INCLUDE_PYTHON3)
+C_RELEASE_FLAGS   = -Wall -Wextra -Wshadow -pedantic -fopenmp -O3 -g -fno-omit-frame-pointer -std=c11 $(INCLUDE_PYTHON3)
 C_DEBUG_FLAGS     = -Wall -Wextra -Wshadow -pedantic -fopenmp -g -O2 -fsanitize=address -std=c11 $(INCLUDE_PYTHON3)
-C_TEST_FLAGS     = -Wall -Wextra -Wshadow -pedantic -fopenmp -g -O2 -fsanitize=address -std=c11 $(INCLUDE_PYTHON3)
+C_TEST_FLAGS     = -Wall -Wextra -Wshadow -pedantic -fopenmp -O3 -g -fno-omit-frame-pointer -std=c11 $(INCLUDE_PYTHON3)
 
-CXX_RELEASE_FLAGS = -Wall -Wextra -Wshadow -pedantic -fopenmp -O3 -fomit-frame-pointer -std=c++17 $(INCLUDE_PYTHON3)
+CXX_RELEASE_FLAGS = -Wall -Wextra -Wshadow -pedantic -fopenmp -O3 -g -fno-omit-frame-pointer -std=c++17 $(INCLUDE_PYTHON3)
 CXX_DEBUG_FLAGS   = -Wall -Wextra -Wshadow -pedantic -fopenmp -g -O2 -fsanitize=address -std=c++17 $(INCLUDE_PYTHON3)
-CXX_TEST_FLAGS   = -Wall -Wextra -Wshadow -pedantic -fopenmp -g -O2 -fsanitize=address -std=c++17 $(INCLUDE_PYTHON3)
+CXX_TEST_FLAGS   = -Wall -Wextra -Wshadow -pedantic -fopenmp -O3 -g -fno-omit-frame-pointer -std=c++17 $(INCLUDE_PYTHON3)
 
 # Linker options. Add libraries you want to link against here.
 LINK_PYTHON3=`pkg-config --libs python3-embed`
-RELEASE_LINK_FLAGS = -L$(LIB_DIR) -fopenmp -ldl $(LINK_PYTHON3)
-DEBUG_LINK_FLAGS = -L$(LIB_DIR) -fsanitize=address -fopenmp -ldl $(LINK_PYTHON3)
-TEST_LINK_FLAGS = -L$(LIB_DIR) -fsanitize=address -fopenmp -ldl $(LINK_PYTHON3)
+LINK_FLINT = -lflint -lmpfr -lgmp -lm
+LINK_BOOST = -lboost_filesystem -lboost_program_options -lboost_python310
+RELEASE_LINK_FLAGS = -L$(LIB_DIR) -fopenmp -ldl $(LINK_PYTHON3) $(LINK_FLINT) $(LINK_BOOST)
+DEBUG_LINK_FLAGS = -L$(LIB_DIR) -fsanitize=address -fopenmp -ldl $(LINK_PYTHON3) $(LINK_FLINT) $(LINK_BOOST)
+TEST_LINK_FLAGS = -L$(LIB_DIR) -fopenmp -ldl $(LINK_PYTHON3) $(LINK_FLINT) $(LINK_BOOST)
 
 # Output file name
 OUTPUT = PROLEAD
@@ -59,7 +63,7 @@ OUTPUT = PROLEAD
 ##          CORE (do not touch)            ##
 #############################################
 
-.PHONY: all release debug clean help compile directories check
+.PHONY: all release debug clean help compile directories check test
 
 HELP_MESSAGE = Simply use any combination of 'make {debug, release, test, help, clean}'. Just calling 'make' will build release and debug. By adding 'V=1' prints more verbose output.
 
@@ -90,6 +94,7 @@ endif
 
 # list all .c and .cpp files
 C_LIST := $(foreach dir,$(SRC_DIRS),$(patsubst $(dir)/%,$(OUTPUT_DIRECTORY)/$(OBJ_DIR)/$(dir)/%,$(shell find $(dir) -name "*.c")))
+C_LIST := $(filter-out $(EXCLUDED_FILES),$(C_LIST))
 CXX_LIST := $(foreach dir,$(SRC_DIRS),$(patsubst $(dir)/%,$(OUTPUT_DIRECTORY)/$(OBJ_DIR)/$(dir)/%,$(shell find $(dir) -name "*.cpp")))
 
 # create object file names in the obj directory

README.md

@@ -2,6 +2,15 @@
 This repository contains the source code for the papers <a href="https://tches.iacr.org/index.php/TCHES/article/view/9822">PROLEAD - A Probing-Based Hardware Leakage Detection Tool</a> and <a href="https://eprint.iacr.org/2023/034.pdf">PROLEAD_SW - Probing-Based Software Leakage Detection for ARM Binaries</a>.
 For a quick start, we recommend to watch the quick start guides on our <a href="https://www.youtube.com/channel/UCTCuC2NMxaFPtDb4yGHHwTg">Youtube Channel</a> or to read the <a href="https://github.com/ChairImpSec/PROLEAD/wiki/Hardware-beginner's-guide">Hardware beginner's guide</a> or <a href="https://github.com/ChairImpSec/PROLEAD/wiki/Software-beginner's-guide">Software beginner's guide</a> .
 
+## News
+We are excited to announce the release of PROLEADv3, an enhanced and extended version of the original PROLEAD tool. This new version includes several significant features:
+- Evaluation of side-channel resistance under the RR d-probing model
+- Assessment of security against combined adversaries capable of injecting faults and probing wires
+- Support for .json files for configuration and library management, replacing the previous custom file format
+- More granular settings to precisely define adversarial capabilities
+
+We acknowledge that only a few examples are currently available and that full documentation is still in progress. We're working to provide both as quickly as possible. In the meantime, if you have any questions about using PROLEAD, please don't hesitate to reach out to us.
+
 ## Features
 PROLEAD allows to analyze the robust probing security of masked implementations provided as a Verilog netlist or ARM binary. In particular, PROLEAD supports the following features:
 

config.json

@@ -0,0 +1,54 @@
+{
+  "performance": {
+    "max_number_of_threads": "half",
+    "minimize_probing_sets": "aggressive",
+    "number_of_entries_in_report": 10
+  },
+  "simulation": {
+    "groups": [
+      "4'h$",
+      "4'h0"
+    ],
+    "number_of_clock_cycles": 3,
+    "output_shares": [
+      "share1[3:0]",
+      "share2[3:0]",
+      "share3[3:0]"
+    ],
+    "expected_output": [
+      "4'h$",
+      "4'hC"
+    ],
+    "input_sequence": [
+      {
+        "signals": [
+          {
+            "name": "sboxIn1[3:0]",
+            "value": "group_in0[3:0]"
+          },
+          {
+            "name": "sboxIn2[3:0]",
+            "value": "group_in1[3:0]"
+          },
+          {
+            "name": "sboxIn3[3:0]",
+            "value": "group_in2[3:0]"
+          },
+          {
+            "name": "en",
+            "value": "1'b1"
+          }
+        ]
+      }
+    ],
+    "number_of_simulations": 1536000,
+    "number_of_simulations_per_step": 128000
+  },
+  "hardware": {
+    "clock_signal_name": "clk"
+  },
+  "side_channel_analysis": {
+    "order": 1,
+    "transitional_leakage": true
+  }
+}

design.v

@@ -1,7 +1,6 @@
 // Taken from: examples\PRESENT_Sbox_TI_d1_Uniform\gate\design.v
 
-module circuit ( clk, en, sboxIn1, sboxIn2, sboxIn3, share1, share2, share3
- );
+module circuit ( clk, en, sboxIn1, sboxIn2, sboxIn3, share1, share2, share3);
   input [3:0] sboxIn1;
   input [3:0] sboxIn2;
   input [3:0] sboxIn3;
@@ -164,24 +163,24 @@ module circuit ( clk, en, sboxIn1, sboxIn2, sboxIn3, share1, share2, share3
   MUX2_X1 y3_U4 ( .A(g3Reg[2]), .B(g3Out[2]), .S(en), .Z(y3_n12) );
   MUX2_X1 y3_U3 ( .A(g3Reg[1]), .B(g3Out[1]), .S(en), .Z(y3_n11) );
   MUX2_X1 y3_U2 ( .A(g3Reg[0]), .B(g3Out[0]), .S(en), .Z(y3_n10) );
-DFF_X1 y3_s_current_state_reg_0_ ( .D(y3_n10), .CK(clk), .Q(g3Reg[0]) , .QN() );
-DFF_X1 y3_s_current_state_reg_1_ ( .D(y3_n11), .CK(clk), .Q(g3Reg[1]) , .QN() );
-DFF_X1 y3_s_current_state_reg_2_ ( .D(y3_n12), .CK(clk), .Q(g3Reg[2]) , .QN() );
-DFF_X1 y3_s_current_state_reg_3_ ( .D(y3_n13), .CK(clk), .Q(g3Reg[3]) , .QN() );
+  DFF_X1 y3_s_current_state_reg_0_ ( .D(y3_n10), .CK(clk), .Q(g3Reg[0]) , .QN() );
+  DFF_X1 y3_s_current_state_reg_1_ ( .D(y3_n11), .CK(clk), .Q(g3Reg[1]) , .QN() );
+  DFF_X1 y3_s_current_state_reg_2_ ( .D(y3_n12), .CK(clk), .Q(g3Reg[2]) , .QN() );
+  DFF_X1 y3_s_current_state_reg_3_ ( .D(y3_n13), .CK(clk), .Q(g3Reg[3]) , .QN() );
   MUX2_X1 y2_U5 ( .A(g2Reg[3]), .B(g2Out[3]), .S(en), .Z(y2_n14) );
   MUX2_X1 y2_U4 ( .A(g2Reg[2]), .B(g2Out[2]), .S(en), .Z(y2_n15) );
   MUX2_X1 y2_U3 ( .A(g2Reg[1]), .B(g2Out[1]), .S(en), .Z(y2_n16) );
   MUX2_X1 y2_U2 ( .A(g2Reg[0]), .B(g2Out[0]), .S(en), .Z(y2_n17) );
-DFF_X1 y2_s_current_state_reg_0_ ( .D(y2_n17), .CK(clk), .Q(g2Reg[0]) , .QN() );
-DFF_X1 y2_s_current_state_reg_1_ ( .D(y2_n16), .CK(clk), .Q(g2Reg[1]) , .QN() );
-DFF_X1 y2_s_current_state_reg_2_ ( .D(y2_n15), .CK(clk), .Q(g2Reg[2]) , .QN() );
-DFF_X1 y2_s_current_state_reg_3_ ( .D(y2_n14), .CK(clk), .Q(g2Reg[3]) , .QN() );
+  DFF_X1 y2_s_current_state_reg_0_ ( .D(y2_n17), .CK(clk), .Q(g2Reg[0]) , .QN() );
+  DFF_X1 y2_s_current_state_reg_1_ ( .D(y2_n16), .CK(clk), .Q(g2Reg[1]) , .QN() );
+  DFF_X1 y2_s_current_state_reg_2_ ( .D(y2_n15), .CK(clk), .Q(g2Reg[2]) , .QN() );
+  DFF_X1 y2_s_current_state_reg_3_ ( .D(y2_n14), .CK(clk), .Q(g2Reg[3]) , .QN() );
   MUX2_X1 y1_U5 ( .A(g1Reg[3]), .B(g1Out[3]), .S(en), .Z(y1_n14) );
   MUX2_X1 y1_U4 ( .A(g1Reg[2]), .B(g1Out[2]), .S(en), .Z(y1_n15) );
   MUX2_X1 y1_U3 ( .A(g1Reg[1]), .B(g1Out[1]), .S(en), .Z(y1_n16) );
   MUX2_X1 y1_U2 ( .A(g1Reg[0]), .B(g1Out[0]), .S(en), .Z(y1_n17) );
-DFF_X1 y1_s_current_state_reg_0_ ( .D(y1_n17), .CK(clk), .Q(g1Reg[0]) , .QN() );
-DFF_X1 y1_s_current_state_reg_1_ ( .D(y1_n16), .CK(clk), .Q(g1Reg[1]) , .QN() );
-DFF_X1 y1_s_current_state_reg_2_ ( .D(y1_n15), .CK(clk), .Q(g1Reg[2]) , .QN() );
-DFF_X1 y1_s_current_state_reg_3_ ( .D(y1_n14), .CK(clk), .Q(g1Reg[3]) , .QN() );
+  DFF_X1 y1_s_current_state_reg_0_ ( .D(y1_n17), .CK(clk), .Q(g1Reg[0]) , .QN() );
+  DFF_X1 y1_s_current_state_reg_1_ ( .D(y1_n16), .CK(clk), .Q(g1Reg[1]) , .QN() );
+  DFF_X1 y1_s_current_state_reg_2_ ( .D(y1_n15), .CK(clk), .Q(g1Reg[2]) , .QN() );
+  DFF_X1 y1_s_current_state_reg_3_ ( .D(y1_n14), .CK(clk), .Q(g1Reg[3]) , .QN() );
 endmodule